whitequark 27b47faf16 hdl.ast: add Value.{as_signed,as_unsigned}. ... Before this commit, there was no way to do so besides creating and assigning an intermediate signal, which could not be extracted into a helper function due to Module statefulness. Fixes #292.		2020-02-06 18:27:55 +00:00
..
__init__.py	Initial commit.	2018-12-12 03:18:44 +00:00
pysim.py	hdl.ast: add Value.{as_signed,as_unsigned}.	2020-02-06 18:27:55 +00:00
rtlil.py	hdl.ast: add Value.{as_signed,as_unsigned}.	2020-02-06 18:27:55 +00:00
verilog.py	back.verilog: remove $verilog_initial_trigger after proc_prune.	2019-10-28 10:11:41 +00:00