44711b7d08
Requres every elaboratable to inherit from Elaboratable, but still accepts ones that do not, with a warning. Fixes #3.
95 lines
3.4 KiB
Python
95 lines
3.4 KiB
Python
from .. import *
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__all__ = ["MultiReg", "ResetSynchronizer"]
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class MultiReg(Elaboratable):
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"""Resynchronise a signal to a different clock domain.
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Consists of a chain of flip-flops. Eliminates metastabilities at the output, but provides
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no other guarantee as to the safe domain-crossing of a signal.
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Parameters
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----------
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i : Signal(), in
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Signal to be resynchronised
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o : Signal(), out
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Signal connected to synchroniser output
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odomain : str
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Name of output clock domain
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n : int
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Number of flops between input and output.
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reset : int
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Reset value of the flip-flops. On FPGAs, even if ``reset_less`` is True, the MultiReg is
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still set to this value during initialization.
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reset_less : bool
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If True (the default), this MultiReg is unaffected by ``odomain`` reset.
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See "Note on Reset" below.
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Platform override
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-----------------
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Define the ``get_multi_reg`` platform metehod to override the implementation of MultiReg,
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e.g. to instantiate library cells directly.
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Note on Reset
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-------------
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MultiReg is non-resettable by default. Usually this is the safest option; on FPGAs
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the MultiReg will still be initialized to its ``reset`` value when the FPGA loads its
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configuration.
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However, in designs where the value of the MultiReg must be valid immediately after reset,
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consider setting ``reset_less`` to False if any of the following is true:
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- You are targeting an ASIC, or an FPGA that does not allow arbitrary initial flip-flop states;
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- Your design features warm (non-power-on) resets of ``odomain``, so the one-time
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initialization at power on is insufficient;
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- Your design features a sequenced reset, and the MultiReg must maintain its reset value until
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``odomain`` reset specifically is deasserted.
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MultiReg is reset by the ``odomain`` reset only.
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"""
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def __init__(self, i, o, odomain="sync", n=2, reset=0, reset_less=True):
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self.i = i
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self.o = o
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self.odomain = odomain
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self._regs = [Signal(self.i.shape(), name="cdc{}".format(i),
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reset=reset, reset_less=reset_less, attrs={"no_retiming": True})
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for i in range(n)]
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def elaborate(self, platform):
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if hasattr(platform, "get_multi_reg"):
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return platform.get_multi_reg(self)
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m = Module()
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for i, o in zip((self.i, *self._regs), self._regs):
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m.d[self.odomain] += o.eq(i)
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m.d.comb += self.o.eq(self._regs[-1])
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return m
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class ResetSynchronizer(Elaboratable):
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def __init__(self, arst, domain="sync", n=2):
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self.arst = arst
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self.domain = domain
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self._regs = [Signal(name="arst{}".format(i), reset=1,
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attrs={"no_retiming": True})
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for i in range(n)]
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def elaborate(self, platform):
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if hasattr(platform, "get_reset_sync"):
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return platform.get_reset_sync(self)
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m = Module()
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m.domains += ClockDomain("_reset_sync", async_reset=True)
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for i, o in zip((0, *self._regs), self._regs):
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m.d._reset_sync += o.eq(i)
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m.d.comb += [
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ClockSignal("_reset_sync").eq(ClockSignal(self.domain)),
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ResetSignal("_reset_sync").eq(self.arst),
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ResetSignal(self.domain).eq(self._regs[-1])
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]
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return m
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