whitequark e3a1d05f23 back.rtlil: fix handling of certain nested arrays. ... This triggers on code like: c1 = Signal() c2 = Signal() c3 = Signal() v1 = Array([Const(1, 8), Const(2, 8)])[c1] v2 = Array([Const(3, 8), Const(4, 8)])[c2] v3 = Array([v1, v2])[c3] Fixes #226.		2019-09-24 18:32:26 +00:00
..
__init__.py	Initial commit.	2018-12-12 03:18:44 +00:00
pysim.py	hdl.ast: rename nbits to width.	2019-09-20 15:36:25 +00:00
rtlil.py	back.rtlil: fix handling of certain nested arrays.	2019-09-24 18:32:26 +00:00
verilog.py	build.plat: strip internal attributes from Verilog output.	2019-09-24 14:56:00 +00:00