20 lines
415 B
Python
20 lines
415 B
Python
from nmigen import *
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from nmigen.cli import main
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m = Module()
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cd_por = ClockDomain(reset_less=True)
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cd_sync = ClockDomain()
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m.domains += cd_por, cd_sync
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delay = Signal(max=255, reset=255)
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with m.If(delay != 0):
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m.d.por += delay.eq(delay - 1)
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m.d.comb += [
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ClockSignal().eq(cd_por.clk),
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ResetSignal().eq(delay == 0),
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]
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if __name__ == "__main__":
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main(m.lower(platform=None), ports=[cd_por.clk])
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