whitequark 49758a3a0c hdl.ast: prohibit shifts by signed value. ... These are not desirable in a HDL, and currently elaborate to broken RTLIL (after YosysHQ/yosys#1551); prohibit them completely, like we already do for division and modulo. Fixes #302.		2020-02-01 23:04:25 +00:00
..
__init__.py	Initial commit.	2018-12-12 03:18:44 +00:00
pysim.py	hdl.ast: prohibit shifts by signed value.	2020-02-01 23:04:25 +00:00
rtlil.py	back.rtlil: don't emit wires for empty signals.	2020-01-31 03:38:58 +00:00
verilog.py	back.verilog: remove $verilog_initial_trigger after proc_prune.	2019-10-28 10:11:41 +00:00