whitequark 49758a3a0c hdl.ast: prohibit shifts by signed value. ... These are not desirable in a HDL, and currently elaborate to broken RTLIL (after YosysHQ/yosys#1551); prohibit them completely, like we already do for division and modulo. Fixes #302.		2020-02-01 23:04:25 +00:00
..
__init__.py	Remove everything deprecated in nmigen 0.1.	2020-01-12 13:59:26 +00:00
ast.py	hdl.ast: prohibit shifts by signed value.	2020-02-01 23:04:25 +00:00
cd.py	hdl.cd: add negedge clock domains.	2019-08-31 22:05:48 +00:00
dsl.py	hdl.dsl: don't allow inheriting from Module.	2020-02-01 02:15:45 +00:00
ir.py	build.plat: align pipeline with Fragment.prepare().	2020-02-01 03:26:04 +00:00
mem.py	hdl.mem: fix src_loc_at in ReadPort, WritePort.	2019-12-15 11:46:26 +00:00
rec.py	Remove everything deprecated in nmigen 0.1.	2020-01-12 13:59:26 +00:00
xfrm.py	hdl.ast: warn on unused property statements (Assert, Assume, etc).	2020-02-01 02:03:23 +00:00