4bfe2cde6f
See #790. This commit adds an entirely private API for describing formatting of values that is used in the standard library, in departure from our standing policy of not using private APIs in the standard library. This is a temporary measure intended to get the version 0.4 released faster, as it has been years in the making. It is expected that this API will be made public in the version 0.5 after going through the usual RFC process. This commit only adds VCD lines for fields defined in `lib.data.Layout` when using `sim.pysim`. The emitted RTLIL and Verilog remain the same. It is expected that when `sim.cxxsim` lands, RTLIL/Verilog output will include aliases for layout fields as well. The value representation API also handles formatting of enumerations, with no changes visible to the designer. The implementation of `Signal(decoder=)` is changed as well to use the new API, with full backwards compatibility and no public API changes. Co-authored-by: Wanda <wanda@phinode.net> |
||
|---|---|---|
| .github | ||
| amaranth | ||
| docs | ||
| examples | ||
| tests | ||
| .codecov.yml | ||
| .coveragerc | ||
| .env.toolchain | ||
| .gitattributes | ||
| .gitignore | ||
| CONTRIBUTING.txt | ||
| LICENSE.txt | ||
| pdm_build.py | ||
| pyproject.toml | ||
| README.md | ||
Amaranth HDL (previously nMigen)
The Amaranth project provides an open-source toolchain for developing hardware based on synchronous digital logic using the Python programming language, as well as evaluation board definitions, a System on Chip toolkit, and more. It aims to be easy to learn and use, reduce or eliminate common coding mistakes, and simplify the design of complex hardware with reusable components.
The Amaranth toolchain consists of the Amaranth hardware definition language, the standard library, the simulator, and the build system, covering all steps of a typical FPGA development workflow. At the same time, it does not restrict the designer’s choice of tools: existing industry-standard (System)Verilog or VHDL code can be integrated into an Amaranth-based design flow, or, conversely, Amaranth code can be integrated into an existing Verilog-based design flow.
The development of Amaranth has been supported by LambdaConcept, ChipEleven, and Chipflow.
Introduction
See the Introduction section of the documentation.
Installation
See the Installation section of the documentation.
Supported devices
Amaranth can be used to target any FPGA or ASIC process that accepts behavioral Verilog-2001 as input. It also offers extended support for many FPGA families, providing toolchain integration, abstractions for device-specific primitives, and more. Specifically:
- Lattice iCE40 (toolchains: Yosys+nextpnr, LSE-iCECube2, Synplify-iCECube2);
- Lattice MachXO2 (toolchains: Diamond);
- Lattice MachXO3L (toolchains: Diamond);
- Lattice ECP5 (toolchains: Yosys+nextpnr, Diamond);
- Xilinx Spartan 3A (toolchains: ISE);
- Xilinx Spartan 6 (toolchains: ISE);
- Xilinx 7-series (toolchains: Vivado);
- Xilinx UltraScale (toolchains: Vivado);
- Intel (toolchains: Quartus);
- Quicklogic EOS S3 (toolchains: Yosys+VPR).
FOSS toolchains are listed in bold.
Community
Amaranth has a dedicated IRC channel, #amaranth-lang at libera.chat, which is bridged1 to Matrix at #amaranth-lang:matrix.org. Feel free to join to ask questions about using Amaranth or discuss ongoing development of Amaranth and its related projects.
License
Amaranth is released under the very permissive two-clause BSD license. Under the terms of this license, you are authorized to use Amaranth for closed-source proprietary designs.
-
The same messages appear on IRC and on Matrix, and one can participate in the discussion equally using either communication system. ↩︎