60 lines
1.5 KiB
Python
60 lines
1.5 KiB
Python
from nmigen.fhdl import *
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from nmigen.back import rtlil, verilog
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class Adder:
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def __init__(self, width):
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self.a = Signal(width)
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self.b = Signal(width)
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self.o = Signal(width)
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def get_fragment(self, platform):
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f = Module()
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f.comb += self.o.eq(self.a + self.b)
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return f.lower(platform)
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class Subtractor:
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def __init__(self, width):
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self.a = Signal(width)
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self.b = Signal(width)
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self.o = Signal(width)
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def get_fragment(self, platform):
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f = Module()
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f.comb += self.o.eq(self.a - self.b)
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return f.lower(platform)
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class ALU:
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def __init__(self, width):
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self.op = Signal()
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self.a = Signal(width)
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self.b = Signal(width)
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self.o = Signal(width)
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self.add = Adder(width)
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self.sub = Subtractor(width)
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def get_fragment(self, platform):
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f = Module()
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f.submodules.add = self.add
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f.submodules.sub = self.sub
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f.comb += [
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self.add.a.eq(self.a),
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self.sub.a.eq(self.a),
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self.add.b.eq(self.b),
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self.sub.b.eq(self.b),
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]
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with f.If(self.op):
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f.comb += self.o.eq(self.sub.o)
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with f.Else():
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f.comb += self.o.eq(self.add.o)
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return f.lower(platform)
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alu = ALU(width=16)
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frag = alu.get_fragment(platform=None)
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# print(rtlil.convert(frag, ports=[alu.op, alu.a, alu.b, alu.o]))
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print(verilog.convert(frag, ports=[alu.op, alu.a, alu.b, alu.o, alu.add.o, alu.sub.o]))
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