Catherine 525c7e2be0 back.rtlil: do not translate empty subfragments at all. ... It was thought previously (by me) that adding a wire that does nothing to an empty subfragment is enough to prevent it from being treated as a blackbox. This is enough for Yosys but not Vivado. Another workaround could probably be used that satisfies both, but instead let's just not translate any empty subfragments. This doesn't account for the case of the empty toplevel, but that does not seem worth addressing. Fixes #899.		2023-09-05 06:29:57 +00:00
..
__init__.py	Rename nMigen to Amaranth HDL.	2021-12-10 10:34:13 +00:00
cxxrtl.py	hdl.ast: support division and modulo with negative divisor.	2021-12-11 10:25:48 +00:00
rtlil.py	back.rtlil: do not translate empty subfragments at all.	2023-09-05 06:29:57 +00:00
verilog.py	back.{verilog,rtlil}: in convert(), accept a Component without ports.	2023-09-04 19:05:49 +00:00