132 lines
5.1 KiB
Python
132 lines
5.1 KiB
Python
from ..tools import deprecated
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from .. import *
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__all__ = ["FFSynchronizer", "ResetSynchronizer"]
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# TODO(nmigen-0.2): remove this
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__all__ += ["MultiReg"]
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class FFSynchronizer(Elaboratable):
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"""Resynchronise a signal to a different clock domain.
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Consists of a chain of flip-flops. Eliminates metastabilities at the output, but provides
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no other guarantee as to the safe domain-crossing of a signal.
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Parameters
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----------
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i : Signal(n), in
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Signal to be resynchronised.
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o : Signal(n), out
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Signal connected to synchroniser output.
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o_domain : str
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Name of output clock domain.
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stages : int
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Number of synchronization stages between input and output. The lowest safe number is 2,
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with higher numbers reducing MTBF further, at the cost of increased latency.
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reset : int
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Reset value of the flip-flops. On FPGAs, even if ``reset_less`` is True,
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the :class:`FFSynchronizer` is still set to this value during initialization.
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reset_less : bool
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If True (the default), this :class:`FFSynchronizer` is unaffected by ``o_domain`` reset.
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See "Note on Reset" below.
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Platform override
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-----------------
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Define the ``get_ff_sync`` platform method to override the implementation of
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:class:`FFSynchronizer`, e.g. to instantiate library cells directly.
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Note on Reset
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-------------
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:class:`FFSynchronizer` is non-resettable by default. Usually this is the safest option;
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on FPGAs the :class:`FFSynchronizer` will still be initialized to its ``reset`` value when
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the FPGA loads its configuration.
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However, in designs where the value of the :class:`FFSynchronizer` must be valid immediately
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after reset, consider setting ``reset_less`` to False if any of the following is true:
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- You are targeting an ASIC, or an FPGA that does not allow arbitrary initial flip-flop states;
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- Your design features warm (non-power-on) resets of ``o_domain``, so the one-time
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initialization at power on is insufficient;
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- Your design features a sequenced reset, and the :class:`FFSynchronizer` must maintain
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its reset value until ``o_domain`` reset specifically is deasserted.
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:class:`FFSynchronizer` is reset by the ``o_domain`` reset only.
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"""
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def __init__(self, i, o, *, o_domain="sync", stages=2, reset=0, reset_less=True):
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self.i = i
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self.o = o
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self._reset = reset
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self._reset_less = reset_less
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self._o_domain = o_domain
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self._stages = stages
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def elaborate(self, platform):
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if hasattr(platform, "get_ff_sync"):
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return platform.get_ff_sync(self)
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m = Module()
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flops = [Signal(self.i.shape(), name="stage{}".format(index),
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reset=self._reset, reset_less=self._reset_less)
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for index in range(self._stages)]
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for i, o in zip((self.i, *flops), flops):
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m.d[self._o_domain] += o.eq(i)
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m.d.comb += self.o.eq(flops[-1])
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return m
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# TODO(nmigen-0.2): remove this
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MultiReg = deprecated("instead of `MultiReg`, use `FFSynchronizer`")(FFSynchronizer)
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class ResetSynchronizer(Elaboratable):
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"""Synchronize deassertion of a clock domain reset.
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The reset of the clock domain driven by the :class:`ResetSynchronizer` is asserted
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asynchronously and deasserted synchronously, eliminating metastability during deassertion.
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The driven clock domain could use a reset that is asserted either synchronously or
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asynchronously; a reset is always deasserted synchronously. A domain with an asynchronously
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asserted reset is useful if the clock of the domain may be gated, yet the domain still
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needs to be reset promptly; otherwise, synchronously asserted reset (the default) should
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be used.
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Parameters
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----------
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arst : Signal(1), out
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Asynchronous reset signal, to be synchronized.
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domain : str
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Name of clock domain to reset.
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stages : int, >=2
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Number of synchronization stages between input and output. The lowest safe number is 2,
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with higher numbers reducing MTBF further, at the cost of increased deassertion latency.
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Platform override
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-----------------
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Define the ``get_reset_sync`` platform method to override the implementation of
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:class:`ResetSynchronizer`, e.g. to instantiate library cells directly.
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"""
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def __init__(self, arst, *, domain="sync", stages=2):
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self.arst = arst
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self._domain = domain
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self._stages = stages
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def elaborate(self, platform):
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if hasattr(platform, "get_reset_sync"):
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return platform.get_reset_sync(self)
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m = Module()
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m.domains += ClockDomain("reset_sync", async_reset=True, local=True)
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flops = [Signal(1, name="stage{}".format(index), reset=1)
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for index in range(self._stages)]
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for i, o in zip((0, *flops), flops):
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m.d.reset_sync += o.eq(i)
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m.d.comb += [
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ClockSignal("reset_sync").eq(ClockSignal(self._domain)),
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ResetSignal("reset_sync").eq(self.arst),
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ResetSignal(self._domain).eq(flops[-1])
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]
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return m
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