whitequark 53bb4300a3 build.plat: strip internal attributes from Verilog output. ... Although useful for debugging, most external tools often complain about such attributes (with notable exception of Vivado). As such, it is better to emit Verilog with these attributes into a separate file such as `design.debug.v` and only emit the attributes that were explicitly placed by the user to `design.v`. This still leaves the (*init*) attribute. See #220 for details.		2019-09-24 14:56:00 +00:00
..
__init__.py	Initial commit.	2018-12-12 03:18:44 +00:00
pysim.py	hdl.ast: rename nbits to width.	2019-09-20 15:36:25 +00:00
rtlil.py	back.rtlil: give predictable names to anonymous subfragments.	2019-09-23 12:48:02 +00:00
verilog.py	build.plat: strip internal attributes from Verilog output.	2019-09-24 14:56:00 +00:00