b65e11f38f
Before this commit, each simulation engine (which is only pysim at
the moment, but also cxxsim soon) was a subclass of SimulatorCore,
and every simulation engine module would essentially duplicate
the complete structure of a simulator, with code partially shared.
This was a really bad idea: it was inconvenient to use, with
downstream code having to branch between e.g. PySettle and CxxSettle;
it had no well-defined external interface; it had multiple virtually
identical entry points; and it had no separation between simulation
algorithms and glue code.
This commit completely rearranges simulation code.
1. sim._base defines internal simulation interfaces. The clarity of
these internal interfaces is important because simulation
engines mix and match components to provide a consistent API
regardless of the chosen engine.
2. sim.core defines the external simulation interface: the commands
and the simulator facade. The facade provides a single entry
point and, when possible, validates or lowers user input.
It also imports built-in simulation engines by their symbolic
name, avoiding eager imports of pyvcd or ctypes.
3. sim.xxxsim (currently, only sim.pysim) defines the simulator
implementation: time and state management, process scheduling,
and waveform dumping.
The new simulator structure has none of the downsides of the old one.
See #324.
232 lines
7.8 KiB
Python
232 lines
7.8 KiB
Python
# nmigen: UnusedElaboratable=no
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from nmigen.hdl import *
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from nmigen.sim import *
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from nmigen.lib.cdc import *
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from .utils import *
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class FFSynchronizerTestCase(FHDLTestCase):
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def test_stages_wrong(self):
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with self.assertRaisesRegex(TypeError,
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r"^Synchronization stage count must be a positive integer, not 0$"):
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FFSynchronizer(Signal(), Signal(), stages=0)
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with self.assertRaisesRegex(ValueError,
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r"^Synchronization stage count may not safely be less than 2$"):
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FFSynchronizer(Signal(), Signal(), stages=1)
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def test_basic(self):
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i = Signal()
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o = Signal()
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frag = FFSynchronizer(i, o)
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sim = Simulator(frag)
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sim.add_clock(1e-6)
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def process():
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self.assertEqual((yield o), 0)
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yield i.eq(1)
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yield Tick()
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self.assertEqual((yield o), 0)
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yield Tick()
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self.assertEqual((yield o), 0)
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yield Tick()
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self.assertEqual((yield o), 1)
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sim.add_process(process)
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sim.run()
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def test_reset_value(self):
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i = Signal(reset=1)
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o = Signal()
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frag = FFSynchronizer(i, o, reset=1)
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sim = Simulator(frag)
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sim.add_clock(1e-6)
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def process():
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self.assertEqual((yield o), 1)
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yield i.eq(0)
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yield Tick()
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self.assertEqual((yield o), 1)
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yield Tick()
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self.assertEqual((yield o), 1)
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yield Tick()
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self.assertEqual((yield o), 0)
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sim.add_process(process)
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sim.run()
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class AsyncFFSynchronizerTestCase(FHDLTestCase):
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def test_stages_wrong(self):
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with self.assertRaisesRegex(TypeError,
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r"^Synchronization stage count must be a positive integer, not 0$"):
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ResetSynchronizer(Signal(), stages=0)
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with self.assertRaisesRegex(ValueError,
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r"^Synchronization stage count may not safely be less than 2$"):
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ResetSynchronizer(Signal(), stages=1)
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def test_edge_wrong(self):
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with self.assertRaisesRegex(ValueError,
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r"^AsyncFFSynchronizer async edge must be one of 'pos' or 'neg', not 'xxx'$"):
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AsyncFFSynchronizer(Signal(), Signal(), o_domain="sync", async_edge="xxx")
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def test_pos_edge(self):
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i = Signal()
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o = Signal()
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m = Module()
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m.domains += ClockDomain("sync")
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m.submodules += AsyncFFSynchronizer(i, o)
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sim = Simulator(m)
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sim.add_clock(1e-6)
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def process():
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# initial reset
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self.assertEqual((yield i), 0)
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self.assertEqual((yield o), 1)
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yield Tick(); yield Delay(1e-8)
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self.assertEqual((yield o), 1)
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yield Tick(); yield Delay(1e-8)
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self.assertEqual((yield o), 0)
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yield Tick(); yield Delay(1e-8)
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self.assertEqual((yield o), 0)
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yield Tick(); yield Delay(1e-8)
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yield i.eq(1)
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yield Delay(1e-8)
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self.assertEqual((yield o), 1)
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yield Tick(); yield Delay(1e-8)
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self.assertEqual((yield o), 1)
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yield i.eq(0)
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yield Tick(); yield Delay(1e-8)
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self.assertEqual((yield o), 1)
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yield Tick(); yield Delay(1e-8)
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self.assertEqual((yield o), 0)
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yield Tick(); yield Delay(1e-8)
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self.assertEqual((yield o), 0)
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yield Tick(); yield Delay(1e-8)
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sim.add_process(process)
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with sim.write_vcd("test.vcd"):
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sim.run()
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def test_neg_edge(self):
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i = Signal(reset=1)
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o = Signal()
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m = Module()
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m.domains += ClockDomain("sync")
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m.submodules += AsyncFFSynchronizer(i, o, async_edge="neg")
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sim = Simulator(m)
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sim.add_clock(1e-6)
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def process():
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# initial reset
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self.assertEqual((yield i), 1)
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self.assertEqual((yield o), 1)
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yield Tick(); yield Delay(1e-8)
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self.assertEqual((yield o), 1)
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yield Tick(); yield Delay(1e-8)
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self.assertEqual((yield o), 0)
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yield Tick(); yield Delay(1e-8)
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self.assertEqual((yield o), 0)
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yield Tick(); yield Delay(1e-8)
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yield i.eq(0)
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yield Delay(1e-8)
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self.assertEqual((yield o), 1)
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yield Tick(); yield Delay(1e-8)
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self.assertEqual((yield o), 1)
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yield i.eq(1)
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yield Tick(); yield Delay(1e-8)
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self.assertEqual((yield o), 1)
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yield Tick(); yield Delay(1e-8)
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self.assertEqual((yield o), 0)
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yield Tick(); yield Delay(1e-8)
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self.assertEqual((yield o), 0)
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yield Tick(); yield Delay(1e-8)
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sim.add_process(process)
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with sim.write_vcd("test.vcd"):
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sim.run()
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class ResetSynchronizerTestCase(FHDLTestCase):
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def test_stages_wrong(self):
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with self.assertRaisesRegex(TypeError,
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r"^Synchronization stage count must be a positive integer, not 0$"):
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ResetSynchronizer(Signal(), stages=0)
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with self.assertRaisesRegex(ValueError,
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r"^Synchronization stage count may not safely be less than 2$"):
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ResetSynchronizer(Signal(), stages=1)
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def test_basic(self):
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arst = Signal()
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m = Module()
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m.domains += ClockDomain("sync")
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m.submodules += ResetSynchronizer(arst)
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s = Signal(reset=1)
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m.d.sync += s.eq(0)
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sim = Simulator(m)
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sim.add_clock(1e-6)
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def process():
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# initial reset
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self.assertEqual((yield s), 1)
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yield Tick(); yield Delay(1e-8)
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self.assertEqual((yield s), 1)
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yield Tick(); yield Delay(1e-8)
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self.assertEqual((yield s), 1)
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yield Tick(); yield Delay(1e-8)
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self.assertEqual((yield s), 0)
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yield Tick(); yield Delay(1e-8)
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yield arst.eq(1)
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yield Delay(1e-8)
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self.assertEqual((yield s), 0)
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yield Tick(); yield Delay(1e-8)
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self.assertEqual((yield s), 1)
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yield arst.eq(0)
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yield Tick(); yield Delay(1e-8)
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self.assertEqual((yield s), 1)
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yield Tick(); yield Delay(1e-8)
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self.assertEqual((yield s), 1)
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yield Tick(); yield Delay(1e-8)
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self.assertEqual((yield s), 0)
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yield Tick(); yield Delay(1e-8)
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sim.add_process(process)
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with sim.write_vcd("test.vcd"):
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sim.run()
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# TODO: test with distinct clocks
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class PulseSynchronizerTestCase(FHDLTestCase):
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def test_stages_wrong(self):
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with self.assertRaisesRegex(TypeError,
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r"^Synchronization stage count must be a positive integer, not 0$"):
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PulseSynchronizer("w", "r", stages=0)
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with self.assertRaisesRegex(ValueError,
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r"^Synchronization stage count may not safely be less than 2$"):
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PulseSynchronizer("w", "r", stages=1)
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def test_smoke(self):
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m = Module()
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m.domains += ClockDomain("sync")
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ps = m.submodules.dut = PulseSynchronizer("sync", "sync")
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sim = Simulator(m)
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sim.add_clock(1e-6)
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def process():
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yield ps.i.eq(0)
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# TODO: think about reset
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for n in range(5):
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yield Tick()
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# Make sure no pulses are generated in quiescent state
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for n in range(3):
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yield Tick()
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self.assertEqual((yield ps.o), 0)
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# Check conservation of pulses
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accum = 0
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for n in range(10):
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yield ps.i.eq(1 if n < 4 else 0)
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yield Tick()
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accum += yield ps.o
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self.assertEqual(accum, 4)
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sim.add_process(process)
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sim.run()
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