Catherine ecba1a1863 back.rtlil: put hierarchy in module name instead of an attribute. ... The attribute sees essentially no use and the information is much better served by putting it in the module name. In addition this means that the entire tree can be renamed simply by renaming the top module. Tools like GTKWave show the names of the instances, not the modules, so they are not affected by the longer names.		2023-09-13 12:46:46 +00:00
..
__init__.py	Rename nMigen to Amaranth HDL.	2021-12-10 10:34:13 +00:00
cxxrtl.py	hdl.ast: support division and modulo with negative divisor.	2021-12-11 10:25:48 +00:00
rtlil.py	back.rtlil: put hierarchy in module name instead of an attribute.	2023-09-13 12:46:46 +00:00
verilog.py	back.{verilog,rtlil}: in convert(), accept a Component without ports.	2023-09-04 19:05:49 +00:00