50 lines
2 KiB
Python
50 lines
2 KiB
Python
import warnings
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from .._toolchain.yosys import *
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from ..hdl import ir
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from . import rtlil
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__all__ = ["YosysError", "convert", "convert_fragment"]
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def _convert_rtlil_text(rtlil_text, *, strip_internal_attrs=False, write_verilog_opts=()):
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# this version requirement needs to be synchronized with the one in setup.py!
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yosys = find_yosys(lambda ver: ver >= (0, 10))
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yosys_version = yosys.version()
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script = []
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script.append("read_ilang <<rtlil\n{}\nrtlil".format(rtlil_text))
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script.append("proc -nomux")
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script.append("memory_collect")
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if strip_internal_attrs:
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attr_map = []
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attr_map.append("-remove generator")
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attr_map.append("-remove top")
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attr_map.append("-remove src")
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attr_map.append("-remove amaranth.hierarchy")
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attr_map.append("-remove amaranth.decoding")
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script.append("attrmap {}".format(" ".join(attr_map)))
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script.append("attrmap -modattr {}".format(" ".join(attr_map)))
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script.append("write_verilog -norename {}".format(" ".join(write_verilog_opts)))
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return yosys.run(["-q", "-"], "\n".join(script),
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# At the moment, Yosys always shows a warning indicating that not all processes can be
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# translated to Verilog. We carefully emit only the processes that *can* be translated, and
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# squash this warning. Once Yosys' write_verilog pass is fixed, we should remove this.
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ignore_warnings=True)
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def convert_fragment(*args, strip_internal_attrs=False, **kwargs):
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rtlil_text, name_map = rtlil.convert_fragment(*args, **kwargs)
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return _convert_rtlil_text(rtlil_text, strip_internal_attrs=strip_internal_attrs), name_map
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def convert(elaboratable, name="top", platform=None, *, ports, emit_src=True,
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strip_internal_attrs=False, **kwargs):
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fragment = ir.Fragment.get(elaboratable, platform).prepare(ports=ports, **kwargs)
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verilog_text, name_map = convert_fragment(fragment, name, emit_src=emit_src, strip_internal_attrs=strip_internal_attrs)
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return verilog_text
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