162 lines
6.6 KiB
Python
162 lines
6.6 KiB
Python
from .tools import *
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from ..hdl.ast import *
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from ..hdl.dsl import *
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from ..back.pysim import *
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from ..lib.fifo import *
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class FIFOSmokeTestCase(FHDLTestCase):
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def assertSyncFIFOWorks(self, fifo):
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with Simulator(fifo) as sim:
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sim.add_clock(1e-6)
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def process():
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yield from fifo.write(1)
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yield from fifo.write(2)
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yield
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self.assertEqual((yield from fifo.read()), 1)
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self.assertEqual((yield from fifo.read()), 2)
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sim.add_sync_process(process)
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sim.run()
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def test_sync_fwft(self):
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fifo = SyncFIFO(width=8, depth=4, fwft=True)
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self.assertSyncFIFOWorks(SyncFIFO(width=8, depth=4))
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def test_sync_not_fwft(self):
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fifo = SyncFIFO(width=8, depth=4, fwft=False)
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self.assertSyncFIFOWorks(SyncFIFO(width=8, depth=4))
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def test_sync_buffered(self):
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fifo = SyncFIFO(width=8, depth=4, fwft=True)
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self.assertSyncFIFOWorks(SyncFIFOBuffered(width=8, depth=4))
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class SyncFIFOInvariants:
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def __init__(self, fifo):
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self.fifo = fifo
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def get_fragment(self, platform):
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m = Module()
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m.submodules.dut = fifo = self.fifo
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with m.If(Fell(ResetSignal())):
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m.d.comb += [
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Assert(fifo.level == 0),
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Assert(~fifo.readable),
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Assert(fifo.writable),
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]
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with m.Elif(~ResetSignal()):
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m.d.comb += Assert(fifo.level == (Past(fifo.level)
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+ (Past(fifo.writable) & Past(fifo.we) & ~Past(fifo.replace))
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- (Past(fifo.readable) & Past(fifo.re))))
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with m.If(fifo.level != 0):
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m.d.comb += Assert(fifo.readable)
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with m.If(fifo.level != fifo.depth):
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m.d.comb += Assert(fifo.writable)
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with m.If(Past(1)):
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with m.If(~Past(fifo.re)):
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# Unless `re` is asserted, output should not change, other than for the case of
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# an empty FWFT queue, or an FWFT queue with a single entry being replaced.
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if fifo.fwft:
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with m.If((fifo.level == 1) & Past(fifo.we) &
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(Past(fifo.writable) | Past(fifo.replace))):
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m.d.comb += Assert(fifo.dout == Past(fifo.din))
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with m.Else():
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m.d.comb += Assert(fifo.dout == Past(fifo.dout))
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else:
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m.d.comb += Assert(fifo.dout == Past(fifo.dout))
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return m.lower(platform)
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class SyncFIFOBufferedInvariants:
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def __init__(self, fifo):
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self.fifo = fifo
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def get_fragment(self, platform):
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m = Module()
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m.submodules.dut = fifo = self.fifo
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with m.If(Fell(ResetSignal())):
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m.d.comb += [
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Assert(fifo.level == 0),
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Assert(~fifo.readable),
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Assert(fifo.writable),
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]
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with m.Elif(~ResetSignal()):
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m.d.comb += Assert(fifo.level == (Past(fifo.level)
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+ (Past(fifo.writable) & Past(fifo.we))
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- (Past(fifo.readable) & Past(fifo.re))))
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with m.If(fifo.level == 0):
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m.d.comb += Assert(~fifo.readable)
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with m.If(fifo.level == 1):
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# When there is one entry in the queue, it might be either in the inner unbuffered
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# queue memory, or in its output register.
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with m.If(Past(fifo.readable)):
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# On the previous cycle, there was an entry in output register.
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with m.If(Past(fifo.level) == 1):
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# It was the only entry in the queue, so it's only there if it was
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# not read.
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m.d.comb += Assert(fifo.readable == ~Past(fifo.re))
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with m.Else():
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# There were more entries in the queue, which would refil the output
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# register, if necessary.
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m.d.comb += Assert(fifo.readable)
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with m.Elif(~Fell(ResetSignal(), 1)):
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# On the previous cycle, there was no entry in the output register, so there is
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# one only if it was written two cycles back.
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m.d.comb += Assert(fifo.readable == Past(fifo.we, 2))
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with m.If(fifo.level > 1):
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m.d.comb += Assert(fifo.readable)
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with m.If(fifo.level != fifo.depth):
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m.d.comb += Assert(fifo.writable)
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with m.If(~Past(fifo.re)):
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# Unless `re` is asserted, output should not change, other than for the case of
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# an empty FWFT queue, where it changes with latency 1.
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with m.If(fifo.readable & ~Past(fifo.readable) &
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Past(fifo.we, 2) & Past(fifo.writable, 2)):
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m.d.comb += Assert(fifo.dout == Past(fifo.din, 2))
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with m.Else():
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m.d.comb += Assert(fifo.dout == Past(fifo.dout))
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return m.lower(platform)
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class FIFOFormalCase(FHDLTestCase):
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def test_sync_fwft_pot(self):
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fifo = SyncFIFO(width=8, depth=4, fwft=True)
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self.assertFormal(SyncFIFOInvariants(fifo),
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mode="prove", depth=fifo.depth * 2)
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def test_sync_fwft_npot(self):
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fifo = SyncFIFO(width=8, depth=5, fwft=True)
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self.assertFormal(SyncFIFOInvariants(fifo),
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mode="prove", depth=fifo.depth * 2)
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def test_sync_not_fwft_pot(self):
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fifo = SyncFIFO(width=8, depth=4, fwft=False)
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self.assertFormal(SyncFIFOInvariants(fifo),
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mode="prove", depth=fifo.depth * 2)
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def test_sync_not_fwft_npot(self):
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fifo = SyncFIFO(width=8, depth=5, fwft=False)
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self.assertFormal(SyncFIFOInvariants(fifo),
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mode="prove", depth=fifo.depth * 2)
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def test_sync_buffered_pot(self):
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fifo = SyncFIFOBuffered(width=8, depth=4)
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self.assertFormal(SyncFIFOBufferedInvariants(fifo),
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mode="prove", depth=fifo.depth * 2)
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def test_sync_buffered_potp1(self):
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fifo = SyncFIFOBuffered(width=8, depth=5)
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self.assertFormal(SyncFIFOBufferedInvariants(fifo),
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mode="prove", depth=fifo.depth * 2)
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def test_sync_buffered_potm1(self):
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fifo = SyncFIFOBuffered(width=8, depth=3)
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self.assertFormal(SyncFIFOBufferedInvariants(fifo),
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mode="prove", depth=fifo.depth * 2)
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