Wanda ae36b596bb hdl.mem: Switch to first-class IR representation for memories. ... Fixes #611.		2024-01-17 08:10:28 +00:00
..
__init__.py	Rename nMigen to Amaranth HDL.	2021-12-10 10:34:13 +00:00
cxxrtl.py	Pyupgrade to 3.8+. NFCI	2023-11-14 13:07:21 +00:00
rtlil.py	hdl.mem: Switch to first-class IR representation for memories.	2024-01-17 08:10:28 +00:00
verilog.py	back.verilog: require Yosys >=0.35.	2023-11-21 14:52:42 +00:00