whitequark 378e924280 hdl.ast: rename nbits to width. ... Also, replace `bits, sign = x.shape()` with more idiomatic `width, signed = x.shape()`. This unifies all properties corresponding to `len(x)` to `x.width`. (Not all values have a `width` property.) Fixes #210.		2019-09-20 15:36:25 +00:00
..
__init__.py	Initial commit.	2018-12-12 03:18:44 +00:00
pysim.py	hdl.ast: rename nbits to width.	2019-09-20 15:36:25 +00:00
rtlil.py	hdl.ast: rename nbits to width.	2019-09-20 15:36:25 +00:00
verilog.py	back: return name map from convert_fragment().	2019-09-11 23:22:12 +00:00