32 lines
831 B
Python
32 lines
831 B
Python
from types import SimpleNamespace
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from nmigen import *
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from nmigen.back import rtlil, verilog, pysim
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class GPIO:
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def __init__(self, pins, bus):
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self.pins = pins
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self.bus = bus
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def get_fragment(self, platform):
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m = Module()
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m.d.comb += self.bus.dat_r.eq(self.pins[self.bus.adr])
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with m.If(self.bus.we):
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m.d.sync += self.pins[self.bus.adr].eq(self.bus.dat_w)
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return m.lower(platform)
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# TODO: use Record
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bus = SimpleNamespace(
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adr=Signal(max=8),
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dat_r=Signal(),
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dat_w=Signal(),
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we=Signal()
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)
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pins = Signal(8)
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gpio = GPIO(Array(pins), bus)
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frag = gpio.get_fragment(platform=None)
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# print(rtlil.convert(frag, ports=[pins, bus.adr, bus.dat_r, bus.dat_w, bus.we]))
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print(verilog.convert(frag, ports=[pins, bus.adr, bus.dat_r, bus.dat_w, bus.we]))
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