amaranth/examples/basic/arst.py
whitequark 5c63177fc2 test: generate examples to verilog as part of unit tests.
This is to make sure 806a62c2 doesn't happen again.
2019-07-08 10:12:26 +00:00

22 lines
535 B
Python

from nmigen import *
from nmigen.cli import main
class ClockDivisor(Elaboratable):
def __init__(self, factor):
self.v = Signal(factor)
self.o = Signal()
def elaborate(self, platform):
m = Module()
m.d.sync += self.v.eq(self.v + 1)
m.d.comb += self.o.eq(self.v[-1])
return m
if __name__ == "__main__":
m = Module()
m.domains.sync = sync = ClockDomain("sync", async_reset=True)
m.submodules.ctr = ctr = ClockDivisor(factor=16)
main(m, ports=[ctr.o, sync.clk])