7df70059d1
The redesign introduces no fundamental incompatibilities, but it does
involve minor breaking changes:
* The simulator commands were moved from hdl.ast to back.pysim
(instead of only being reexported from back.pysim).
* back.pysim.DeadlineError was removed.
Summary of changes:
* The new simulator compiles HDL to Python code and is >6x faster.
(The old one compiled HDL to lots of Python lambdas.)
* The new simulator is a straightforward, rigorous implementation
of the Synchronous Reactive Programming paradigm, instead of
a pile of ad-hoc code with no particular design driving it.
* The new simulator never raises DeadlineError, and there is no
limit on the amount of delta cycles.
* The new simulator robustly handles multiclock designs.
* The new simulator can be reset, such that the compiled design
can be reused, which can save significant runtime with large
designs.
* Generators can no longer be added as processes, since that would
break reset(); only generator functions may be. If necessary,
they may be added by wrapping them into a generator function;
a deprecated fallback does just that. This workaround will raise
an exception if the simulator is reset and restarted.
* The new simulator does not depend on Python extensions.
(The old one required bitarray, which did not provide wheels.)
Fixes #28.
Fixes #34.
Fixes #160.
Fixes #161.
Fixes #215.
Fixes #242.
Fixes #262.
34 lines
846 B
Python
34 lines
846 B
Python
from nmigen import *
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from nmigen.back import rtlil, verilog, pysim
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class Counter(Elaboratable):
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def __init__(self, width):
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self.v = Signal(width, reset=2**width-1)
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self.o = Signal()
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self.en = Signal()
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def elaborate(self, platform):
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m = Module()
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m.d.sync += self.v.eq(self.v + 1)
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m.d.comb += self.o.eq(self.v[-1])
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return EnableInserter(self.en)(m)
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ctr = Counter(width=16)
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print(verilog.convert(ctr, ports=[ctr.o, ctr.en]))
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sim = pysim.Simulator(ctr)
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sim.add_clock(1e-6)
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def ce_proc():
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yield; yield; yield
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yield ctr.en.eq(1)
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yield; yield; yield
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yield ctr.en.eq(0)
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yield; yield; yield
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yield ctr.en.eq(1)
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sim.add_sync_process(ce_proc)
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with sim.write_vcd("ctrl.vcd", "ctrl.gtkw", traces=[ctr.en, ctr.v, ctr.o]):
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sim.run_until(100e-6, run_passive=True)
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