whitequark 6cd9f7db19 compat.genlib.resetsync: add shim for AsyncResetSynchronizer.		2019-01-26 18:24:36 +00:00
..
fhdl	test.compat: reenable tests converting to Verilog.	2019-01-26 15:29:09 +00:00
genlib	compat.genlib.resetsync: add shim for AsyncResetSynchronizer.	2019-01-26 18:24:36 +00:00
sim	compat.sim: fix deprecated stdlib import.	2019-01-26 15:26:54 +00:00
__init__.py	compat: import genlib.record from Migen.	2018-12-18 20:04:22 +00:00