whitequark 6d417568ad back.pysim: only extract signal names if VCD is requested. ... This commit also fixes an issue introduced in 2606ee33 that regressed simulator startup time and bloated VCD files. (It's actually about 10% faster now than *before* the regression was introduced.)		2020-07-08 08:33:45 +00:00
..
__init__.py	Initial commit.	2018-12-12 03:18:44 +00:00
cxxrtl.py	_yosys→_toolchain.yosys	2020-07-02 18:26:08 +00:00
pysim.py	back.pysim: only extract signal names if VCD is requested.	2020-07-08 08:33:45 +00:00
rtlil.py	back.rtlil: handle signed and large Instance parameters correctly.	2020-05-19 23:33:14 +00:00
verilog.py	_yosys→_toolchain.yosys	2020-07-02 18:26:08 +00:00