6f44438e58
The new intermediate representation will enable global analyses on Amaranth code without lowering it to another representation such as RTLIL. This commit also changes the RTLIL builder to use the new IR. Co-authored-by: Wanda <wanda@phinode.net>
785 lines
22 KiB
Python
785 lines
22 KiB
Python
# amaranth: UnusedElaboratable=no
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import warnings
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from amaranth.hdl._ast import *
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from amaranth.hdl._cd import *
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from amaranth.hdl._dsl import *
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from amaranth.hdl._ir import *
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from amaranth.hdl._xfrm import *
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from amaranth.hdl._mem import *
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from amaranth.hdl._mem import MemoryInstance
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from .utils import *
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from amaranth._utils import _ignore_deprecated
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class DomainRenamerTestCase(FHDLTestCase):
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def setUp(self):
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self.s1 = Signal()
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self.s2 = Signal()
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self.s3 = Signal()
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self.s4 = Signal()
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self.s5 = Signal()
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self.c1 = Signal()
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def test_rename_signals(self):
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f = Fragment()
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f.add_statements(
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"comb",
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self.s1.eq(ClockSignal()),
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ResetSignal().eq(self.s2),
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self.s4.eq(ClockSignal("other")),
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self.s5.eq(ResetSignal("other")),
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)
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f.add_statements(
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"sync",
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self.s3.eq(0),
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)
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f.add_driver(self.s1, "comb")
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f.add_driver(self.s2, "comb")
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f.add_driver(self.s3, "sync")
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f = DomainRenamer("pix")(f)
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self.assertRepr(f.statements["comb"], """
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(
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(eq (sig s1) (clk pix))
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(eq (rst pix) (sig s2))
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(eq (sig s4) (clk other))
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(eq (sig s5) (rst other))
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)
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""")
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self.assertRepr(f.statements["pix"], """
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(
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(eq (sig s3) (const 1'd0))
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)
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""")
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self.assertFalse("sync" in f.statements)
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self.assertEqual(f.drivers, {
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"comb": SignalSet((self.s1, self.s2)),
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"pix": SignalSet((self.s3,)),
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})
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def test_rename_multi(self):
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f = Fragment()
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f.add_statements(
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"comb",
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self.s1.eq(ClockSignal()),
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self.s2.eq(ResetSignal("other")),
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)
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f = DomainRenamer({"sync": "pix", "other": "pix2"})(f)
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self.assertRepr(f.statements["comb"], """
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(
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(eq (sig s1) (clk pix))
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(eq (sig s2) (rst pix2))
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)
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""")
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def test_rename_cd(self):
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cd_sync = ClockDomain()
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cd_pix = ClockDomain()
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f = Fragment()
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f.add_domains(cd_sync, cd_pix)
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f = DomainRenamer("ext")(f)
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self.assertEqual(cd_sync.name, "ext")
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self.assertEqual(f.domains, {
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"ext": cd_sync,
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"pix": cd_pix,
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})
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def test_rename_cd_preserves_allow_reset_less(self):
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cd_pix = ClockDomain(reset_less=True)
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f = Fragment()
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f.add_domains(cd_pix)
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f.add_statements(
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"comb",
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self.s1.eq(ResetSignal(allow_reset_less=True)),
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)
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f = DomainRenamer("pix")(f)
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f = DomainLowerer()(f)
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self.assertRepr(f.statements["comb"], """
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(
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(eq (sig s1) (const 1'd0))
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)
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""")
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def test_rename_cd_subfragment(self):
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cd_sync = ClockDomain()
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cd_pix = ClockDomain()
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f1 = Fragment()
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f1.add_domains(cd_sync, cd_pix)
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f2 = Fragment()
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f2.add_domains(cd_sync)
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f1.add_subfragment(f2)
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f1 = DomainRenamer("ext")(f1)
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self.assertEqual(cd_sync.name, "ext")
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self.assertEqual(f1.domains, {
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"ext": cd_sync,
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"pix": cd_pix,
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})
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def test_rename_mem_ports(self):
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m = Module()
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mem = Memory(depth=4, width=16)
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m.submodules.mem = mem
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mem.read_port(domain="a")
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mem.read_port(domain="b")
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mem.write_port(domain="c")
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f = Fragment.get(m, None)
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f = DomainRenamer({"a": "d", "c": "e"})(f)
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mem = f.subfragments[0][0]
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self.assertIsInstance(mem, MemoryInstance)
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self.assertEqual(mem._read_ports[0]._domain, "d")
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self.assertEqual(mem._read_ports[1]._domain, "b")
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self.assertEqual(mem._write_ports[0]._domain, "e")
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def test_rename_wrong_to_comb(self):
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with self.assertRaisesRegex(ValueError,
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r"^Domain 'sync' may not be renamed to 'comb'$"):
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DomainRenamer("comb")
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def test_rename_wrong_from_comb(self):
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with self.assertRaisesRegex(ValueError,
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r"^Domain 'comb' may not be renamed$"):
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DomainRenamer({"comb": "sync"})
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class DomainLowererTestCase(FHDLTestCase):
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def setUp(self):
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self.s = Signal()
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def test_lower_clk(self):
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sync = ClockDomain()
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f = Fragment()
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f.add_domains(sync)
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f.add_statements(
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"comb",
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self.s.eq(ClockSignal("sync"))
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)
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f = DomainLowerer()(f)
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self.assertRepr(f.statements["comb"], """
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(
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(eq (sig s) (sig clk))
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)
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""")
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def test_lower_rst(self):
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sync = ClockDomain()
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f = Fragment()
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f.add_domains(sync)
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f.add_statements(
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"comb",
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self.s.eq(ResetSignal("sync"))
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)
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f = DomainLowerer()(f)
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self.assertRepr(f.statements["comb"], """
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(
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(eq (sig s) (sig rst))
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)
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""")
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def test_lower_rst_reset_less(self):
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sync = ClockDomain(reset_less=True)
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f = Fragment()
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f.add_domains(sync)
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f.add_statements(
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"comb",
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self.s.eq(ResetSignal("sync", allow_reset_less=True))
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)
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f = DomainLowerer()(f)
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self.assertRepr(f.statements["comb"], """
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(
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(eq (sig s) (const 1'd0))
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)
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""")
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def test_lower_drivers(self):
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sync = ClockDomain()
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pix = ClockDomain()
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f = Fragment()
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f.add_domains(sync, pix)
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f.add_driver(ClockSignal("pix"), "comb")
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f.add_driver(ResetSignal("pix"), "sync")
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f = DomainLowerer()(f)
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self.assertEqual(f.drivers, {
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"comb": SignalSet((pix.clk,)),
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"sync": SignalSet((pix.rst,))
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})
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def test_lower_wrong_domain(self):
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f = Fragment()
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f.add_statements(
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"comb",
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self.s.eq(ClockSignal("xxx"))
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)
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with self.assertRaisesRegex(DomainError,
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r"^Signal \(clk xxx\) refers to nonexistent domain 'xxx'$"):
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DomainLowerer()(f)
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def test_lower_wrong_reset_less_domain(self):
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sync = ClockDomain(reset_less=True)
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f = Fragment()
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f.add_domains(sync)
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f.add_statements(
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"comb",
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self.s.eq(ResetSignal("sync"))
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)
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with self.assertRaisesRegex(DomainError,
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r"^Signal \(rst sync\) refers to reset of reset-less domain 'sync'$"):
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DomainLowerer()(f)
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class ResetInserterTestCase(FHDLTestCase):
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def setUp(self):
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self.s1 = Signal()
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self.s2 = Signal(reset=1)
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self.s3 = Signal(reset=1, reset_less=True)
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self.c1 = Signal()
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def test_reset_default(self):
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f = Fragment()
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f.add_statements(
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"sync",
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self.s1.eq(1)
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)
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f.add_driver(self.s1, "sync")
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f = ResetInserter(self.c1)(f)
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self.assertRepr(f.statements["sync"], """
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(
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(eq (sig s1) (const 1'd1))
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(switch (sig c1)
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(case 1 (eq (sig s1) (const 1'd0)))
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)
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)
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""")
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def test_reset_cd(self):
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f = Fragment()
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f.add_statements("sync", self.s1.eq(1))
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f.add_statements("pix", self.s2.eq(0))
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f.add_domains(ClockDomain("sync"))
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f.add_driver(self.s1, "sync")
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f.add_driver(self.s2, "pix")
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f = ResetInserter({"pix": self.c1})(f)
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self.assertRepr(f.statements["sync"], """
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(
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(eq (sig s1) (const 1'd1))
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)
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""")
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self.assertRepr(f.statements["pix"], """
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(
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(eq (sig s2) (const 1'd0))
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(switch (sig c1)
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(case 1 (eq (sig s2) (const 1'd1)))
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)
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)
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""")
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def test_reset_value(self):
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f = Fragment()
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f.add_statements("sync", self.s2.eq(0))
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f.add_driver(self.s2, "sync")
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f = ResetInserter(self.c1)(f)
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self.assertRepr(f.statements["sync"], """
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(
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(eq (sig s2) (const 1'd0))
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(switch (sig c1)
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(case 1 (eq (sig s2) (const 1'd1)))
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)
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)
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""")
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def test_reset_less(self):
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f = Fragment()
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f.add_statements("sync", self.s3.eq(0))
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f.add_driver(self.s3, "sync")
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f = ResetInserter(self.c1)(f)
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self.assertRepr(f.statements["sync"], """
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(
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(eq (sig s3) (const 1'd0))
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(switch (sig c1)
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(case 1 )
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)
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)
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""")
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class EnableInserterTestCase(FHDLTestCase):
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def setUp(self):
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self.s1 = Signal()
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self.s2 = Signal()
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self.s3 = Signal()
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self.c1 = Signal()
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def test_enable_default(self):
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f = Fragment()
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f.add_statements("sync", self.s1.eq(1))
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f.add_driver(self.s1, "sync")
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f = EnableInserter(self.c1)(f)
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self.assertRepr(f.statements["sync"], """
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(
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(eq (sig s1) (const 1'd1))
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(switch (sig c1)
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(case 0 (eq (sig s1) (sig s1)))
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)
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)
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""")
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def test_enable_cd(self):
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f = Fragment()
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f.add_statements("sync", self.s1.eq(1))
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f.add_statements("pix", self.s2.eq(0))
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f.add_driver(self.s1, "sync")
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f.add_driver(self.s2, "pix")
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f = EnableInserter({"pix": self.c1})(f)
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self.assertRepr(f.statements["sync"], """
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(
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(eq (sig s1) (const 1'd1))
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)
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""")
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self.assertRepr(f.statements["pix"], """
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(
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(eq (sig s2) (const 1'd0))
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(switch (sig c1)
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(case 0 (eq (sig s2) (sig s2)))
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)
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)
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""")
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def test_enable_subfragment(self):
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f1 = Fragment()
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f1.add_statements("sync", self.s1.eq(1))
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f1.add_driver(self.s1, "sync")
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f2 = Fragment()
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f2.add_statements("sync", self.s2.eq(1))
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f2.add_driver(self.s2, "sync")
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f1.add_subfragment(f2)
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f1 = EnableInserter(self.c1)(f1)
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(f2, _), = f1.subfragments
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self.assertRepr(f1.statements["sync"], """
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(
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(eq (sig s1) (const 1'd1))
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(switch (sig c1)
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(case 0 (eq (sig s1) (sig s1)))
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)
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)
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""")
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self.assertRepr(f2.statements["sync"], """
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(
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(eq (sig s2) (const 1'd1))
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(switch (sig c1)
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(case 0 (eq (sig s2) (sig s2)))
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)
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)
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""")
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def test_enable_read_port(self):
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mem = Memory(width=8, depth=4)
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mem.read_port(transparent=False)
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f = EnableInserter(self.c1)(mem).elaborate(platform=None)
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self.assertRepr(f._read_ports[0]._en, """
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(& (sig mem_r_en) (sig c1))
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""")
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def test_enable_write_port(self):
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mem = Memory(width=8, depth=4)
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mem.write_port(granularity=2)
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f = EnableInserter(self.c1)(mem).elaborate(platform=None)
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self.assertRepr(f._write_ports[0]._en, """
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(m
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(sig c1)
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(sig mem_w_en)
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(const 4'd0)
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)
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""")
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class AssignmentLegalizerTestCase(FHDLTestCase):
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def test_simple(self):
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s1 = Signal(8)
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s2 = Signal(8)
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f = Fragment()
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f.add_statements(
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"sync",
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s1.eq(s2)
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)
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f.add_driver(s1, "sync")
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f = AssignmentLegalizer()(f)
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self.assertRepr(f.statements["sync"], """
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((eq (sig s1) (sig s2)))
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""")
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def test_simple_slice(self):
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s1 = Signal(8)
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s2 = Signal(4)
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f = Fragment()
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f.add_statements(
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"sync",
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s1[2:6].eq(s2)
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)
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f.add_driver(s1, "sync")
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f = AssignmentLegalizer()(f)
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self.assertRepr(f.statements["sync"], """
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((eq (slice (sig s1) 2:6) (sig s2)))
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""")
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def test_simple_part(self):
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s1 = Signal(8)
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s2 = Signal(4)
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s3 = Signal(4)
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f = Fragment()
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f.add_statements(
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"sync",
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s1.bit_select(s3, 4).eq(s2)
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)
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f.add_driver(s1, "sync")
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f = AssignmentLegalizer()(f)
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self.assertRepr(f.statements["sync"], """
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((switch (sig s3)
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(case 0000 (eq (slice (sig s1) 0:4) (sig s2)))
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(case 0001 (eq (slice (sig s1) 1:5) (sig s2)))
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(case 0010 (eq (slice (sig s1) 2:6) (sig s2)))
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(case 0011 (eq (slice (sig s1) 3:7) (sig s2)))
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(case 0100 (eq (slice (sig s1) 4:8) (sig s2)))
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(case 0101 (eq (slice (sig s1) 5:8) (sig s2)))
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(case 0110 (eq (slice (sig s1) 6:8) (sig s2)))
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(case 0111 (eq (slice (sig s1) 7:8) (sig s2)))
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))
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""")
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def test_simple_part_word(self):
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s1 = Signal(8)
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s2 = Signal(4)
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s3 = Signal(4)
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f = Fragment()
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f.add_statements(
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"sync",
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s1.word_select(s3, 4).eq(s2)
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)
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f.add_driver(s1, "sync")
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f = AssignmentLegalizer()(f)
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self.assertRepr(f.statements["sync"], """
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((switch (sig s3)
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(case 0000 (eq (slice (sig s1) 0:4) (sig s2)))
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(case 0001 (eq (slice (sig s1) 4:8) (sig s2)))
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))
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""")
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def test_simple_concat(self):
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s1 = Signal(4)
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s2 = Signal(4)
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s3 = Signal(4)
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s4 = Signal(12)
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f = Fragment()
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f.add_statements(
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"sync",
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Cat(s1, s2, s3).eq(s4)
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)
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f.add_driver(s1, "sync")
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f.add_driver(s2, "sync")
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f.add_driver(s3, "sync")
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f = AssignmentLegalizer()(f)
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self.assertRepr(f.statements["sync"], """
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(
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(eq (sig s1) (slice (sig s4) 0:12))
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(eq (sig s2) (slice (sig s4) 4:12))
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(eq (sig s3) (slice (sig s4) 8:12))
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)
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""")
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def test_simple_concat_narrow(self):
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s1 = Signal(4)
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s2 = Signal(4)
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s3 = Signal(4)
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s4 = Signal(signed(6))
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f = Fragment()
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f.add_statements(
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"sync",
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Cat(s1, s2, s3).eq(s4)
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)
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f.add_driver(s1, "sync")
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f.add_driver(s2, "sync")
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f.add_driver(s3, "sync")
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f = AssignmentLegalizer()(f)
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self.assertRepr(f.statements["sync"], """
|
|
(
|
|
(eq (sig s1) (slice (| (sig s4) (const 12'sd0)) 0:12))
|
|
(eq (sig s2) (slice (| (sig s4) (const 12'sd0)) 4:12))
|
|
(eq (sig s3) (slice (| (sig s4) (const 12'sd0)) 8:12))
|
|
)
|
|
""")
|
|
|
|
def test_simple_operator(self):
|
|
s1 = Signal(8)
|
|
s2 = Signal(8)
|
|
s3 = Signal(8)
|
|
f = Fragment()
|
|
f.add_statements("sync", [
|
|
s1.as_signed().eq(s3),
|
|
s2.as_unsigned().eq(s3),
|
|
])
|
|
f.add_driver(s1, "sync")
|
|
f.add_driver(s2, "sync")
|
|
f = AssignmentLegalizer()(f)
|
|
self.assertRepr(f.statements["sync"], """
|
|
(
|
|
(eq (sig s1) (sig s3))
|
|
(eq (sig s2) (sig s3))
|
|
)
|
|
""")
|
|
|
|
def test_simple_array(self):
|
|
s1 = Signal(8)
|
|
s2 = Signal(8)
|
|
s3 = Signal(8)
|
|
s4 = Signal(8)
|
|
s5 = Signal(8)
|
|
f = Fragment()
|
|
f.add_statements("sync", [
|
|
Array([s1, s2, s3])[s4].eq(s5),
|
|
])
|
|
f.add_driver(s1, "sync")
|
|
f.add_driver(s2, "sync")
|
|
f.add_driver(s3, "sync")
|
|
f = AssignmentLegalizer()(f)
|
|
self.assertRepr(f.statements["sync"], """
|
|
((switch (sig s4)
|
|
(case 00000000 (eq (sig s1) (sig s5)))
|
|
(case 00000001 (eq (sig s2) (sig s5)))
|
|
(case 00000010 (eq (sig s3) (sig s5)))
|
|
))
|
|
""")
|
|
|
|
def test_sliced_slice(self):
|
|
s1 = Signal(12)
|
|
s2 = Signal(4)
|
|
f = Fragment()
|
|
f.add_statements(
|
|
"sync",
|
|
s1[1:11][2:6].eq(s2)
|
|
)
|
|
f.add_driver(s1, "sync")
|
|
f = AssignmentLegalizer()(f)
|
|
self.assertRepr(f.statements["sync"], """
|
|
((eq (slice (sig s1) 3:7) (sig s2)))
|
|
""")
|
|
|
|
def test_sliced_concat(self):
|
|
s1 = Signal(4)
|
|
s2 = Signal(4)
|
|
s3 = Signal(4)
|
|
s4 = Signal(4)
|
|
s5 = Signal(4)
|
|
s6 = Signal(8)
|
|
f = Fragment()
|
|
f.add_statements(
|
|
"sync",
|
|
Cat(s1, s2, s3, s4, s5)[5:14].eq(s6)
|
|
)
|
|
f.add_driver(s1, "sync")
|
|
f.add_driver(s2, "sync")
|
|
f.add_driver(s3, "sync")
|
|
f.add_driver(s4, "sync")
|
|
f.add_driver(s5, "sync")
|
|
f = AssignmentLegalizer()(f)
|
|
self.assertRepr(f.statements["sync"], """
|
|
(
|
|
(eq (slice (sig s2) 1:4) (slice (| (sig s6) (const 9'd0)) 0:9))
|
|
(eq (sig s3) (slice (| (sig s6) (const 9'd0)) 3:9))
|
|
(eq (slice (sig s4) 0:2) (slice (| (sig s6) (const 9'd0)) 7:9))
|
|
)
|
|
""")
|
|
|
|
def test_sliced_part(self):
|
|
s1 = Signal(8)
|
|
s2 = Signal(4)
|
|
s3 = Signal(4)
|
|
f = Fragment()
|
|
f.add_statements(
|
|
"sync",
|
|
s1.bit_select(s3, 4)[1:3].eq(s2)
|
|
)
|
|
f.add_driver(s1, "sync")
|
|
f = AssignmentLegalizer()(f)
|
|
self.assertRepr(f.statements["sync"], """
|
|
((switch (sig s3)
|
|
(case 0000 (eq (slice (sig s1) 1:3) (sig s2)))
|
|
(case 0001 (eq (slice (sig s1) 2:4) (sig s2)))
|
|
(case 0010 (eq (slice (sig s1) 3:5) (sig s2)))
|
|
(case 0011 (eq (slice (sig s1) 4:6) (sig s2)))
|
|
(case 0100 (eq (slice (sig s1) 5:7) (sig s2)))
|
|
(case 0101 (eq (slice (sig s1) 6:8) (sig s2)))
|
|
(case 0110 (eq (slice (sig s1) 7:8) (sig s2)))
|
|
))
|
|
""")
|
|
|
|
def test_sliced_part_word(self):
|
|
s1 = Signal(8)
|
|
s2 = Signal(4)
|
|
s3 = Signal(4)
|
|
f = Fragment()
|
|
f.add_statements(
|
|
"sync",
|
|
s1.word_select(s3, 4)[1:3].eq(s2)
|
|
)
|
|
f.add_driver(s1, "sync")
|
|
f = AssignmentLegalizer()(f)
|
|
self.assertRepr(f.statements["sync"], """
|
|
((switch (sig s3)
|
|
(case 0000 (eq (slice (sig s1) 1:3) (sig s2)))
|
|
(case 0001 (eq (slice (sig s1) 5:7) (sig s2)))
|
|
))
|
|
""")
|
|
|
|
def test_sliced_array(self):
|
|
s1 = Signal(8)
|
|
s2 = Signal(8)
|
|
s3 = Signal(8)
|
|
s4 = Signal(8)
|
|
s5 = Signal(8)
|
|
f = Fragment()
|
|
f.add_statements("sync", [
|
|
Array([s1, s2, s3])[s4][2:7].eq(s5),
|
|
])
|
|
f.add_driver(s1, "sync")
|
|
f.add_driver(s2, "sync")
|
|
f.add_driver(s3, "sync")
|
|
f = AssignmentLegalizer()(f)
|
|
self.assertRepr(f.statements["sync"], """
|
|
((switch (sig s4)
|
|
(case 00000000 (eq (slice (sig s1) 2:7) (sig s5)))
|
|
(case 00000001 (eq (slice (sig s2) 2:7) (sig s5)))
|
|
(case 00000010 (eq (slice (sig s3) 2:7) (sig s5)))
|
|
))
|
|
""")
|
|
|
|
def test_part_slice(self):
|
|
s1 = Signal(8)
|
|
s2 = Signal(4)
|
|
s3 = Signal(4)
|
|
f = Fragment()
|
|
f.add_statements(
|
|
"sync",
|
|
s1[1:7].bit_select(s3, 4).eq(s2)
|
|
)
|
|
f.add_driver(s1, "sync")
|
|
f = AssignmentLegalizer()(f)
|
|
self.assertRepr(f.statements["sync"], """
|
|
((switch (sig s3)
|
|
(case 0000 (eq (slice (sig s1) 1:5) (sig s2)))
|
|
(case 0001 (eq (slice (sig s1) 2:6) (sig s2)))
|
|
(case 0010 (eq (slice (sig s1) 3:7) (sig s2)))
|
|
(case 0011 (eq (slice (sig s1) 4:7) (sig s2)))
|
|
(case 0100 (eq (slice (sig s1) 5:7) (sig s2)))
|
|
(case 0101 (eq (slice (sig s1) 6:7) (sig s2)))
|
|
))
|
|
""")
|
|
|
|
def test_sliced_part_slice(self):
|
|
s1 = Signal(12)
|
|
s2 = Signal(4)
|
|
s3 = Signal(4)
|
|
f = Fragment()
|
|
f.add_statements(
|
|
"sync",
|
|
s1[3:9].bit_select(s3, 4)[1:3].eq(s2)
|
|
)
|
|
f.add_driver(s1, "sync")
|
|
f = AssignmentLegalizer()(f)
|
|
self.assertRepr(f.statements["sync"], """
|
|
((switch (sig s3)
|
|
(case 0000 (eq (slice (sig s1) 4:6) (sig s2)))
|
|
(case 0001 (eq (slice (sig s1) 5:7) (sig s2)))
|
|
(case 0010 (eq (slice (sig s1) 6:8) (sig s2)))
|
|
(case 0011 (eq (slice (sig s1) 7:9) (sig s2)))
|
|
(case 0100 (eq (slice (sig s1) 8:9) (sig s2)))
|
|
))
|
|
""")
|
|
|
|
|
|
def test_sliced_operator(self):
|
|
s1 = Signal(8)
|
|
s2 = Signal(8)
|
|
s3 = Signal(8)
|
|
f = Fragment()
|
|
f.add_statements("sync", [
|
|
s1.as_signed()[2:7].eq(s3),
|
|
s2.as_unsigned()[2:7].eq(s3),
|
|
])
|
|
f.add_driver(s1, "sync")
|
|
f.add_driver(s2, "sync")
|
|
f = AssignmentLegalizer()(f)
|
|
self.assertRepr(f.statements["sync"], """
|
|
(
|
|
(eq (slice (sig s1) 2:7) (sig s3))
|
|
(eq (slice (sig s2) 2:7) (sig s3))
|
|
)
|
|
""")
|
|
|
|
|
|
class _MockElaboratable(Elaboratable):
|
|
def __init__(self):
|
|
self.s1 = Signal()
|
|
|
|
def elaborate(self, platform):
|
|
f = Fragment()
|
|
f.add_statements("sync", self.s1.eq(1))
|
|
f.add_driver(self.s1, "sync")
|
|
return f
|
|
|
|
|
|
class TransformedElaboratableTestCase(FHDLTestCase):
|
|
def setUp(self):
|
|
self.c1 = Signal()
|
|
self.c2 = Signal()
|
|
|
|
def test_getattr(self):
|
|
e = _MockElaboratable()
|
|
te = EnableInserter(self.c1)(e)
|
|
|
|
self.assertIs(te.s1, e.s1)
|
|
|
|
def test_composition(self):
|
|
e = _MockElaboratable()
|
|
te1 = EnableInserter(self.c1)(e)
|
|
te2 = ResetInserter(self.c2)(te1)
|
|
|
|
self.assertIsInstance(te1, TransformedElaboratable)
|
|
self.assertIs(te1, te2)
|
|
|
|
f = Fragment.get(te2, None)
|
|
self.assertRepr(f.statements["sync"], """
|
|
(
|
|
(eq (sig s1) (const 1'd1))
|
|
(switch (sig c1)
|
|
(case 0 (eq (sig s1) (sig s1)))
|
|
)
|
|
(switch (sig c2)
|
|
(case 1 (eq (sig s1) (const 1'd0)))
|
|
)
|
|
)
|
|
""")
|