6fd7cbad0d
`Module` is an object with a lot of complex and sometimes fragile behavior that overrides Python attribute accessors and so on. To prevent user designs from breaking when it is changed, it is not supposed to be inherited from (unlike in Migen), but rather returned from the elaborate() method. This commit makes sure it will not be inherited from by accident (most likely by users familiar with Migen). Fixes #286.
737 lines
22 KiB
Python
737 lines
22 KiB
Python
# nmigen: UnusedElaboratable=no
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from collections import OrderedDict
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from enum import Enum
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from ..hdl.ast import *
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from ..hdl.cd import *
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from ..hdl.dsl import *
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from .utils import *
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class DSLTestCase(FHDLTestCase):
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def setUp(self):
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self.s1 = Signal()
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self.s2 = Signal()
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self.s3 = Signal()
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self.c1 = Signal()
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self.c2 = Signal()
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self.c3 = Signal()
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self.w1 = Signal(4)
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def test_cant_inherit(self):
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with self.assertRaises(SyntaxError,
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msg="Instead of inheriting from `Module`, inherit from `Elaboratable` and "
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"return a `Module` from the `elaborate(self, platform)` method"):
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class ORGate(Module):
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pass
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def test_d_comb(self):
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m = Module()
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m.d.comb += self.c1.eq(1)
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m._flush()
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self.assertEqual(m._driving[self.c1], None)
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self.assertRepr(m._statements, """(
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(eq (sig c1) (const 1'd1))
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)""")
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def test_d_sync(self):
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m = Module()
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m.d.sync += self.c1.eq(1)
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m._flush()
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self.assertEqual(m._driving[self.c1], "sync")
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self.assertRepr(m._statements, """(
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(eq (sig c1) (const 1'd1))
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)""")
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def test_d_pix(self):
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m = Module()
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m.d.pix += self.c1.eq(1)
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m._flush()
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self.assertEqual(m._driving[self.c1], "pix")
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self.assertRepr(m._statements, """(
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(eq (sig c1) (const 1'd1))
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)""")
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def test_d_index(self):
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m = Module()
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m.d["pix"] += self.c1.eq(1)
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m._flush()
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self.assertEqual(m._driving[self.c1], "pix")
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self.assertRepr(m._statements, """(
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(eq (sig c1) (const 1'd1))
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)""")
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def test_d_no_conflict(self):
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m = Module()
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m.d.comb += self.w1[0].eq(1)
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m.d.comb += self.w1[1].eq(1)
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def test_d_conflict(self):
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m = Module()
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with self.assertRaises(SyntaxError,
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msg="Driver-driver conflict: trying to drive (sig c1) from d.sync, but it "
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"is already driven from d.comb"):
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m.d.comb += self.c1.eq(1)
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m.d.sync += self.c1.eq(1)
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def test_d_wrong(self):
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m = Module()
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with self.assertRaises(AttributeError,
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msg="Cannot assign 'd.pix' attribute; did you mean 'd.pix +='?"):
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m.d.pix = None
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def test_d_asgn_wrong(self):
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m = Module()
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with self.assertRaises(SyntaxError,
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msg="Only assignments and property checks may be appended to d.sync"):
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m.d.sync += Switch(self.s1, {})
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def test_comb_wrong(self):
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m = Module()
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with self.assertRaises(AttributeError,
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msg="'Module' object has no attribute 'comb'; did you mean 'd.comb'?"):
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m.comb += self.c1.eq(1)
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def test_sync_wrong(self):
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m = Module()
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with self.assertRaises(AttributeError,
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msg="'Module' object has no attribute 'sync'; did you mean 'd.sync'?"):
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m.sync += self.c1.eq(1)
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def test_attr_wrong(self):
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m = Module()
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with self.assertRaises(AttributeError,
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msg="'Module' object has no attribute 'nonexistentattr'"):
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m.nonexistentattr
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def test_d_suspicious(self):
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m = Module()
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with self.assertWarns(SyntaxWarning,
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msg="Using '<module>.d.submodules' would add statements to clock domain "
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"'submodules'; did you mean <module>.submodules instead?"):
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m.d.submodules += []
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def test_clock_signal(self):
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m = Module()
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m.d.comb += ClockSignal("pix").eq(ClockSignal())
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self.assertRepr(m._statements, """
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(
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(eq (clk pix) (clk sync))
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)
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""")
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def test_reset_signal(self):
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m = Module()
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m.d.comb += ResetSignal("pix").eq(1)
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self.assertRepr(m._statements, """
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(
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(eq (rst pix) (const 1'd1))
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)
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""")
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def test_sample_domain(self):
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m = Module()
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i = Signal()
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o1 = Signal()
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o2 = Signal()
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o3 = Signal()
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m.d.sync += o1.eq(Past(i))
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m.d.pix += o2.eq(Past(i))
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m.d.pix += o3.eq(Past(i, domain="sync"))
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f = m.elaborate(platform=None)
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self.assertRepr(f.statements, """
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(
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(eq (sig o1) (sample (sig i) @ sync[1]))
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(eq (sig o2) (sample (sig i) @ pix[1]))
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(eq (sig o3) (sample (sig i) @ sync[1]))
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)
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""")
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def test_If(self):
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m = Module()
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with m.If(self.s1):
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m.d.comb += self.c1.eq(1)
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m._flush()
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self.assertRepr(m._statements, """
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(
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(switch (cat (sig s1))
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(case 1 (eq (sig c1) (const 1'd1)))
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)
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)
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""")
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def test_If_Elif(self):
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m = Module()
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with m.If(self.s1):
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m.d.comb += self.c1.eq(1)
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with m.Elif(self.s2):
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m.d.sync += self.c2.eq(0)
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m._flush()
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self.assertRepr(m._statements, """
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(
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(switch (cat (sig s1) (sig s2))
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(case -1 (eq (sig c1) (const 1'd1)))
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(case 1- (eq (sig c2) (const 1'd0)))
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)
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)
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""")
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def test_If_Elif_Else(self):
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m = Module()
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with m.If(self.s1):
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m.d.comb += self.c1.eq(1)
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with m.Elif(self.s2):
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m.d.sync += self.c2.eq(0)
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with m.Else():
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m.d.comb += self.c3.eq(1)
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m._flush()
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self.assertRepr(m._statements, """
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(
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(switch (cat (sig s1) (sig s2))
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(case -1 (eq (sig c1) (const 1'd1)))
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(case 1- (eq (sig c2) (const 1'd0)))
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(default (eq (sig c3) (const 1'd1)))
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)
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)
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""")
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def test_If_If(self):
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m = Module()
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with m.If(self.s1):
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m.d.comb += self.c1.eq(1)
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with m.If(self.s2):
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m.d.comb += self.c2.eq(1)
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m._flush()
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self.assertRepr(m._statements, """
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(
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(switch (cat (sig s1))
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(case 1 (eq (sig c1) (const 1'd1)))
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)
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(switch (cat (sig s2))
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(case 1 (eq (sig c2) (const 1'd1)))
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)
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)
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""")
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def test_If_nested_If(self):
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m = Module()
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with m.If(self.s1):
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m.d.comb += self.c1.eq(1)
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with m.If(self.s2):
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m.d.comb += self.c2.eq(1)
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m._flush()
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self.assertRepr(m._statements, """
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(
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(switch (cat (sig s1))
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(case 1 (eq (sig c1) (const 1'd1))
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(switch (cat (sig s2))
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(case 1 (eq (sig c2) (const 1'd1)))
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)
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)
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)
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)
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""")
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def test_If_dangling_Else(self):
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m = Module()
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with m.If(self.s1):
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m.d.comb += self.c1.eq(1)
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with m.If(self.s2):
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m.d.comb += self.c2.eq(1)
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with m.Else():
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m.d.comb += self.c3.eq(1)
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m._flush()
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self.assertRepr(m._statements, """
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(
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(switch (cat (sig s1))
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(case 1
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(eq (sig c1) (const 1'd1))
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(switch (cat (sig s2))
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(case 1 (eq (sig c2) (const 1'd1)))
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)
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)
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(default
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(eq (sig c3) (const 1'd1))
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)
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)
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)
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""")
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def test_Elif_wrong(self):
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m = Module()
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with self.assertRaises(SyntaxError,
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msg="Elif without preceding If"):
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with m.Elif(self.s2):
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pass
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def test_Else_wrong(self):
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m = Module()
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with self.assertRaises(SyntaxError,
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msg="Else without preceding If/Elif"):
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with m.Else():
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pass
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def test_If_wide(self):
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m = Module()
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with m.If(self.w1):
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m.d.comb += self.c1.eq(1)
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m._flush()
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self.assertRepr(m._statements, """
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(
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(switch (cat (b (sig w1)))
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(case 1 (eq (sig c1) (const 1'd1)))
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)
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)
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""")
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def test_If_signed_suspicious(self):
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m = Module()
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with self.assertWarns(SyntaxWarning,
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msg="Signed values in If/Elif conditions usually result from inverting Python "
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"booleans with ~, which leads to unexpected results: ~True is -2, which is "
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"truthful. Replace `~flag` with `not flag`. (If this is a false positive, "
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"silence this warning with `m.If(x)` → `m.If(x.bool())`.)"):
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with m.If(~True):
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pass
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def test_Elif_signed_suspicious(self):
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m = Module()
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with m.If(0):
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pass
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with self.assertWarns(SyntaxWarning,
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msg="Signed values in If/Elif conditions usually result from inverting Python "
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"booleans with ~, which leads to unexpected results: ~True is -2, which is "
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"truthful. Replace `~flag` with `not flag`. (If this is a false positive, "
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"silence this warning with `m.If(x)` → `m.If(x.bool())`.)"):
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with m.Elif(~True):
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pass
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def test_if_If_Elif_Else(self):
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m = Module()
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with self.assertRaises(SyntaxError,
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msg="`if m.If(...):` does not work; use `with m.If(...)`"):
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if m.If(0):
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pass
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with m.If(0):
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pass
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with self.assertRaises(SyntaxError,
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msg="`if m.Elif(...):` does not work; use `with m.Elif(...)`"):
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if m.Elif(0):
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pass
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with self.assertRaises(SyntaxError,
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msg="`if m.Else(...):` does not work; use `with m.Else(...)`"):
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if m.Else():
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pass
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def test_Switch(self):
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m = Module()
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with m.Switch(self.w1):
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with m.Case(3):
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m.d.comb += self.c1.eq(1)
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with m.Case("11--"):
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m.d.comb += self.c2.eq(1)
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m._flush()
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self.assertRepr(m._statements, """
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(
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(switch (sig w1)
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(case 0011 (eq (sig c1) (const 1'd1)))
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(case 11-- (eq (sig c2) (const 1'd1)))
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)
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)
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""")
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def test_Switch_default_Case(self):
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m = Module()
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with m.Switch(self.w1):
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with m.Case(3):
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m.d.comb += self.c1.eq(1)
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with m.Case():
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m.d.comb += self.c2.eq(1)
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m._flush()
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self.assertRepr(m._statements, """
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(
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(switch (sig w1)
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(case 0011 (eq (sig c1) (const 1'd1)))
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(default (eq (sig c2) (const 1'd1)))
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)
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)
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""")
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def test_Switch_default_Default(self):
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m = Module()
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with m.Switch(self.w1):
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with m.Case(3):
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m.d.comb += self.c1.eq(1)
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with m.Default():
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m.d.comb += self.c2.eq(1)
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m._flush()
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self.assertRepr(m._statements, """
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(
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(switch (sig w1)
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(case 0011 (eq (sig c1) (const 1'd1)))
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(default (eq (sig c2) (const 1'd1)))
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)
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)
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""")
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def test_Switch_const_test(self):
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m = Module()
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with m.Switch(1):
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with m.Case(1):
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m.d.comb += self.c1.eq(1)
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m._flush()
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self.assertRepr(m._statements, """
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(
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(switch (const 1'd1)
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(case 1 (eq (sig c1) (const 1'd1)))
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)
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)
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""")
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def test_Switch_enum(self):
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class Color(Enum):
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RED = 1
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BLUE = 2
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m = Module()
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se = Signal(Color)
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with m.Switch(se):
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with m.Case(Color.RED):
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m.d.comb += self.c1.eq(1)
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self.assertRepr(m._statements, """
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(
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(switch (sig se)
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(case 01 (eq (sig c1) (const 1'd1)))
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)
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)
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""")
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def test_Case_width_wrong(self):
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class Color(Enum):
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RED = 0b10101010
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m = Module()
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with m.Switch(self.w1):
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with self.assertRaises(SyntaxError,
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msg="Case pattern '--' must have the same width as switch value (which is 4)"):
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with m.Case("--"):
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pass
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with self.assertWarns(SyntaxWarning,
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msg="Case pattern '10110' is wider than switch value (which has width 4); "
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"comparison will never be true"):
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with m.Case(0b10110):
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pass
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with self.assertWarns(SyntaxWarning,
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msg="Case pattern '10101010' (Color.RED) is wider than switch value "
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"(which has width 4); comparison will never be true"):
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with m.Case(Color.RED):
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pass
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self.assertRepr(m._statements, """
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(
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(switch (sig w1) )
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)
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""")
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def test_Case_bits_wrong(self):
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m = Module()
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with m.Switch(self.w1):
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with self.assertRaises(SyntaxError,
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msg="Case pattern 'abc' must consist of 0, 1, and - (don't care) bits"):
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with m.Case("abc"):
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pass
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def test_Case_pattern_wrong(self):
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m = Module()
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with m.Switch(self.w1):
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with self.assertRaises(SyntaxError,
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msg="Case pattern must be an integer, a string, or an enumeration, not 1.0"):
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with m.Case(1.0):
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pass
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def test_Case_outside_Switch_wrong(self):
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m = Module()
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with self.assertRaises(SyntaxError,
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msg="Case is not permitted outside of Switch"):
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with m.Case():
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pass
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def test_If_inside_Switch_wrong(self):
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m = Module()
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with m.Switch(self.s1):
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with self.assertRaises(SyntaxError,
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msg="If is not permitted directly inside of Switch; "
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"it is permitted inside of Switch Case"):
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with m.If(self.s2):
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pass
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def test_FSM_basic(self):
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a = Signal()
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b = Signal()
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c = Signal()
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m = Module()
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with m.FSM():
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with m.State("FIRST"):
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m.d.comb += a.eq(1)
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m.next = "SECOND"
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with m.State("SECOND"):
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m.d.sync += b.eq(~b)
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with m.If(c):
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m.next = "FIRST"
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m._flush()
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self.assertRepr(m._statements, """
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(
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(switch (sig fsm_state)
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(case 0
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(eq (sig a) (const 1'd1))
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(eq (sig fsm_state) (const 1'd1))
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)
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(case 1
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(eq (sig b) (~ (sig b)))
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(switch (cat (sig c))
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(case 1
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(eq (sig fsm_state) (const 1'd0)))
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)
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)
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)
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)
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""")
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self.assertEqual({repr(k): v for k, v in m._driving.items()}, {
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"(sig a)": None,
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"(sig fsm_state)": "sync",
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"(sig b)": "sync",
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})
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frag = m.elaborate(platform=None)
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fsm = frag.find_generated("fsm")
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self.assertIsInstance(fsm.state, Signal)
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self.assertEqual(fsm.encoding, OrderedDict({
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"FIRST": 0,
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"SECOND": 1,
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}))
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self.assertEqual(fsm.decoding, OrderedDict({
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0: "FIRST",
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1: "SECOND"
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}))
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def test_FSM_reset(self):
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a = Signal()
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m = Module()
|
|
with m.FSM(reset="SECOND"):
|
|
with m.State("FIRST"):
|
|
m.d.comb += a.eq(0)
|
|
m.next = "SECOND"
|
|
with m.State("SECOND"):
|
|
m.next = "FIRST"
|
|
m._flush()
|
|
self.assertRepr(m._statements, """
|
|
(
|
|
(switch (sig fsm_state)
|
|
(case 0
|
|
(eq (sig a) (const 1'd0))
|
|
(eq (sig fsm_state) (const 1'd1))
|
|
)
|
|
(case 1
|
|
(eq (sig fsm_state) (const 1'd0))
|
|
)
|
|
)
|
|
)
|
|
""")
|
|
|
|
def test_FSM_ongoing(self):
|
|
a = Signal()
|
|
b = Signal()
|
|
m = Module()
|
|
with m.FSM() as fsm:
|
|
m.d.comb += b.eq(fsm.ongoing("SECOND"))
|
|
with m.State("FIRST"):
|
|
pass
|
|
m.d.comb += a.eq(fsm.ongoing("FIRST"))
|
|
with m.State("SECOND"):
|
|
pass
|
|
m._flush()
|
|
self.assertEqual(m._generated["fsm"].state.reset, 1)
|
|
self.maxDiff = 10000
|
|
self.assertRepr(m._statements, """
|
|
(
|
|
(eq (sig b) (== (sig fsm_state) (const 1'd0)))
|
|
(eq (sig a) (== (sig fsm_state) (const 1'd1)))
|
|
(switch (sig fsm_state)
|
|
(case 1
|
|
)
|
|
(case 0
|
|
)
|
|
)
|
|
)
|
|
""")
|
|
|
|
def test_FSM_empty(self):
|
|
m = Module()
|
|
with m.FSM():
|
|
pass
|
|
self.assertRepr(m._statements, """
|
|
()
|
|
""")
|
|
|
|
def test_FSM_wrong_domain(self):
|
|
m = Module()
|
|
with self.assertRaises(ValueError,
|
|
msg="FSM may not be driven by the 'comb' domain"):
|
|
with m.FSM(domain="comb"):
|
|
pass
|
|
|
|
def test_FSM_wrong_redefined(self):
|
|
m = Module()
|
|
with m.FSM():
|
|
with m.State("FOO"):
|
|
pass
|
|
with self.assertRaises(SyntaxError,
|
|
msg="FSM state 'FOO' is already defined"):
|
|
with m.State("FOO"):
|
|
pass
|
|
|
|
def test_FSM_wrong_next(self):
|
|
m = Module()
|
|
with self.assertRaises(SyntaxError,
|
|
msg="Only assignment to `m.next` is permitted"):
|
|
m.next
|
|
with self.assertRaises(SyntaxError,
|
|
msg="`m.next = <...>` is only permitted inside an FSM state"):
|
|
m.next = "FOO"
|
|
with self.assertRaises(SyntaxError,
|
|
msg="`m.next = <...>` is only permitted inside an FSM state"):
|
|
with m.FSM():
|
|
m.next = "FOO"
|
|
|
|
def test_If_inside_FSM_wrong(self):
|
|
m = Module()
|
|
with m.FSM():
|
|
with m.State("FOO"):
|
|
pass
|
|
with self.assertRaises(SyntaxError,
|
|
msg="If is not permitted directly inside of FSM; "
|
|
"it is permitted inside of FSM State"):
|
|
with m.If(self.s2):
|
|
pass
|
|
|
|
def test_auto_pop_ctrl(self):
|
|
m = Module()
|
|
with m.If(self.w1):
|
|
m.d.comb += self.c1.eq(1)
|
|
m.d.comb += self.c2.eq(1)
|
|
self.assertRepr(m._statements, """
|
|
(
|
|
(switch (cat (b (sig w1)))
|
|
(case 1 (eq (sig c1) (const 1'd1)))
|
|
)
|
|
(eq (sig c2) (const 1'd1))
|
|
)
|
|
""")
|
|
|
|
def test_submodule_anon(self):
|
|
m1 = Module()
|
|
m2 = Module()
|
|
m1.submodules += m2
|
|
self.assertEqual(m1._anon_submodules, [m2])
|
|
self.assertEqual(m1._named_submodules, {})
|
|
|
|
def test_submodule_anon_multi(self):
|
|
m1 = Module()
|
|
m2 = Module()
|
|
m3 = Module()
|
|
m1.submodules += m2, m3
|
|
self.assertEqual(m1._anon_submodules, [m2, m3])
|
|
self.assertEqual(m1._named_submodules, {})
|
|
|
|
def test_submodule_named(self):
|
|
m1 = Module()
|
|
m2 = Module()
|
|
m1.submodules.foo = m2
|
|
self.assertEqual(m1._anon_submodules, [])
|
|
self.assertEqual(m1._named_submodules, {"foo": m2})
|
|
|
|
def test_submodule_named_index(self):
|
|
m1 = Module()
|
|
m2 = Module()
|
|
m1.submodules["foo"] = m2
|
|
self.assertEqual(m1._anon_submodules, [])
|
|
self.assertEqual(m1._named_submodules, {"foo": m2})
|
|
|
|
def test_submodule_wrong(self):
|
|
m = Module()
|
|
with self.assertRaises(TypeError,
|
|
msg="Trying to add 1, which does not implement .elaborate(), as a submodule"):
|
|
m.submodules.foo = 1
|
|
with self.assertRaises(TypeError,
|
|
msg="Trying to add 1, which does not implement .elaborate(), as a submodule"):
|
|
m.submodules += 1
|
|
|
|
def test_submodule_named_conflict(self):
|
|
m1 = Module()
|
|
m2 = Module()
|
|
m1.submodules.foo = m2
|
|
with self.assertRaises(NameError, msg="Submodule named 'foo' already exists"):
|
|
m1.submodules.foo = m2
|
|
|
|
def test_submodule_get(self):
|
|
m1 = Module()
|
|
m2 = Module()
|
|
m1.submodules.foo = m2
|
|
m3 = m1.submodules.foo
|
|
self.assertEqual(m2, m3)
|
|
|
|
def test_submodule_get_index(self):
|
|
m1 = Module()
|
|
m2 = Module()
|
|
m1.submodules["foo"] = m2
|
|
m3 = m1.submodules["foo"]
|
|
self.assertEqual(m2, m3)
|
|
|
|
def test_submodule_get_unset(self):
|
|
m1 = Module()
|
|
with self.assertRaises(AttributeError, msg="No submodule named 'foo' exists"):
|
|
m2 = m1.submodules.foo
|
|
with self.assertRaises(AttributeError, msg="No submodule named 'foo' exists"):
|
|
m2 = m1.submodules["foo"]
|
|
|
|
def test_domain_named_implicit(self):
|
|
m = Module()
|
|
m.domains += ClockDomain("sync")
|
|
self.assertEqual(len(m._domains), 1)
|
|
|
|
def test_domain_named_explicit(self):
|
|
m = Module()
|
|
m.domains.foo = ClockDomain()
|
|
self.assertEqual(len(m._domains), 1)
|
|
self.assertEqual(m._domains[0].name, "foo")
|
|
|
|
def test_lower(self):
|
|
m1 = Module()
|
|
m1.d.comb += self.c1.eq(self.s1)
|
|
m2 = Module()
|
|
m2.d.comb += self.c2.eq(self.s2)
|
|
m2.d.sync += self.c3.eq(self.s3)
|
|
m1.submodules.foo = m2
|
|
|
|
f1 = m1.elaborate(platform=None)
|
|
self.assertRepr(f1.statements, """
|
|
(
|
|
(eq (sig c1) (sig s1))
|
|
)
|
|
""")
|
|
self.assertEqual(f1.drivers, {
|
|
None: SignalSet((self.c1,))
|
|
})
|
|
self.assertEqual(len(f1.subfragments), 1)
|
|
(f2, f2_name), = f1.subfragments
|
|
self.assertEqual(f2_name, "foo")
|
|
self.assertRepr(f2.statements, """
|
|
(
|
|
(eq (sig c2) (sig s2))
|
|
(eq (sig c3) (sig s3))
|
|
)
|
|
""")
|
|
self.assertEqual(f2.drivers, {
|
|
None: SignalSet((self.c2,)),
|
|
"sync": SignalSet((self.c3,))
|
|
})
|
|
self.assertEqual(len(f2.subfragments), 0)
|