whitequark 71f1f717c4 fhdl.cd: rename ClockDomain signals together with domain.		2018-12-13 15:24:55 +00:00
..
back	fhdl.ir: move Fragment prepare logic from back.rtlil.	2018-12-13 14:34:07 +00:00
compat	compat.genlib.fsm: import/wrap Migen code.	2018-12-13 12:41:19 +00:00
fhdl	fhdl.cd: rename ClockDomain signals together with domain.	2018-12-13 15:24:55 +00:00
genlib	fhdl.ir: implement clock domain propagation.	2018-12-13 11:01:03 +00:00
test	fhdl.cd: rename ClockDomain signals together with domain.	2018-12-13 15:24:55 +00:00
__init__.py	fhdl.ast: add tests for most logic.	2018-12-13 02:06:55 +00:00
tools.py	compat.fhdl.{module,structure}: import/wrap Migen code (WIP).	2018-12-12 15:47:34 +00:00
tracer.py	tracer: add support for Python 3.7.	2018-12-13 02:20:00 +00:00