| .. |
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__init__.py
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hdl.{_ast,_dsl}: factor out the pattern normalization logic.
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2024-04-03 07:34:09 +00:00 |
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_ast.py
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sim: evaluate simulator commands in-place instead of compiling them.
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2024-04-03 14:45:19 +00:00 |
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_cd.py
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amaranth.hdl: start all private names with an underscore.
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2024-01-30 17:20:45 +00:00 |
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_dsl.py
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hdl._mem: implement MemoryData._Row from RFC 62.
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2024-04-03 17:15:02 +00:00 |
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_ir.py
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hdl._ast: Implement Mux in terms of SwitchValue.
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2024-04-03 11:00:58 +00:00 |
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_mem.py
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hdl._mem: implement MemoryData._Row from RFC 62.
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2024-04-03 17:15:02 +00:00 |
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_nir.py
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hdl._ast: Implement Mux in terms of SwitchValue.
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2024-04-03 11:00:58 +00:00 |
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_rec.py
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hdl._ast: deprecate ValueCastable.lowermethod.
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2024-02-13 05:06:06 +00:00 |
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_repr.py
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hdl._ast: fix _value_repr computation.
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2024-03-25 13:53:39 +00:00 |
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_xfrm.py
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hdl._ir: raise an error when an elaboratable is duplicated in hierarchy.
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2024-04-03 10:11:07 +00:00 |
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ast.py
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hdl: remove ValueKey, ValueDict, ValueSet.
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2024-02-11 13:50:06 +00:00 |
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cd.py
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hdl: add missing compatibility shims.
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2024-01-31 02:05:17 +00:00 |
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dsl.py
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hdl: add missing compatibility shims.
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2024-01-31 02:05:17 +00:00 |
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ir.py
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hdl: add missing compatibility shims.
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2024-01-31 02:05:17 +00:00 |
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mem.py
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hdl: add missing compatibility shims.
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2024-01-31 02:05:17 +00:00 |
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rec.py
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hdl.rec: deprecate in favor of lib.data and lib.wiring.
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2023-09-01 04:20:16 +00:00 |
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xfrm.py
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hdl._ir,hdl._nir,back.rtlil: new intermediate representation.
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2024-02-11 09:03:49 +00:00 |
