whitequark 7b25665fde back.pysim: fix behavior of initial cycle for sync processes. ... The current behavior was introduced in 65702719, which was a wrong fix for an issue that was actually fixed in 12e04e4e. This commit effectively reverts 65702719 and 1782b841.		2019-01-25 20:37:56 +00:00
..
__init__.py	fhdl.ast: add tests for most logic.	2018-12-13 02:06:55 +00:00
test_hdl_ast.py	hdl.ast: allow sampling ClockSignal, ResetSignal.	2019-01-17 05:23:06 +00:00
test_hdl_cd.py	hdl.mem: add tests for all error conditions.	2018-12-21 06:07:16 +00:00
test_hdl_dsl.py	hdl.ast: add Past, Stable, Rose, Fell.	2019-01-17 04:31:27 +00:00
test_hdl_ir.py	hdl.ir: allow explicitly requesting flattening.	2019-01-14 17:04:23 +00:00
test_hdl_mem.py	hdl.mem: add DummyPort, for testing and verification.	2019-01-01 03:08:10 +00:00
test_hdl_rec.py	hdl.rec: include record name in error message.	2019-01-01 03:39:12 +00:00
test_hdl_xfrm.py	hdl.xfrm: add SampleLowerer.	2019-01-17 01:41:02 +00:00
test_lib_cdc.py	lib.cdc: fix tests to actually run.	2018-12-29 15:02:44 +00:00
test_lib_coding.py	lib.coding: add GrayEncoder and GrayDecoder.	2019-01-20 02:20:34 +00:00
test_lib_fifo.py	lib.fifo: add AsyncFIFO and AsyncFIFOBuffered.	2019-01-21 16:02:46 +00:00
test_sim.py	back.pysim: fix behavior of initial cycle for sync processes.	2019-01-25 20:37:56 +00:00
tools.py	hdl.xfrm: mark internal registers used in lowering Sample().	2019-01-19 07:27:32 +00:00