35 lines
874 B
Python
35 lines
874 B
Python
from amaranth import *
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from amaranth.sim import *
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from amaranth.back import verilog
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class Counter(Elaboratable):
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def __init__(self, width):
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self.v = Signal(width, init=2**width-1)
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self.o = Signal()
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self.en = Signal()
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def elaborate(self, platform):
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m = Module()
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m.d.sync += self.v.eq(self.v + 1)
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m.d.comb += self.o.eq(self.v[-1])
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return EnableInserter(self.en)(m)
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ctr = Counter(width=16)
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print(verilog.convert(ctr, ports=[ctr.o, ctr.en]))
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sim = Simulator(ctr)
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sim.add_clock(1e-6)
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async def testbench_ce(ctx):
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await ctx.tick().repeat(3)
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ctx.set(ctr.en, 1)
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await ctx.tick().repeat(3)
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ctx.set(ctr.en, 0)
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await ctx.tick().repeat(3)
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ctx.set(ctr.en,1)
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sim.add_testbench(testbench_ce)
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with sim.write_vcd("ctrl.vcd", "ctrl.gtkw", traces=[ctr.en, ctr.v, ctr.o]):
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sim.run_until(100e-6)
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