887 lines
34 KiB
Python
887 lines
34 KiB
Python
import math
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import inspect
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import warnings
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from contextlib import contextmanager
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from bitarray import bitarray
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from vcd import VCDWriter
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from vcd.gtkw import GTKWSave
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from ..tools import flatten
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from ..hdl.ast import *
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from ..hdl.ir import *
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from ..hdl.xfrm import ValueVisitor, StatementVisitor
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__all__ = ["Simulator", "Delay", "Tick", "Passive", "DeadlineError"]
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class DeadlineError(Exception):
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pass
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class _State:
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__slots__ = ("curr", "curr_dirty", "next", "next_dirty")
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def __init__(self):
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self.curr = []
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self.next = []
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self.curr_dirty = bitarray()
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self.next_dirty = bitarray()
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def add(self, value):
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slot = len(self.curr)
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self.curr.append(value)
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self.next.append(value)
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self.curr_dirty.append(True)
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self.next_dirty.append(False)
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return slot
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def set(self, slot, value):
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if self.next[slot] != value:
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self.next_dirty[slot] = True
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self.next[slot] = value
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def commit(self, slot):
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old_value = self.curr[slot]
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new_value = self.next[slot]
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if old_value != new_value:
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self.next_dirty[slot] = False
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self.curr_dirty[slot] = True
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self.curr[slot] = new_value
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return old_value, new_value
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def flush_curr_dirty(self):
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while True:
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try:
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slot = self.curr_dirty.index(True)
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except ValueError:
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break
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self.curr_dirty[slot] = False
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yield slot
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def iter_next_dirty(self):
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start = 0
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while True:
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try:
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slot = self.next_dirty.index(True, start)
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start = slot + 1
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except ValueError:
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break
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yield slot
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normalize = Const.normalize
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class _ValueCompiler(ValueVisitor):
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def on_AnyConst(self, value):
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raise NotImplementedError # :nocov:
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def on_AnySeq(self, value):
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raise NotImplementedError # :nocov:
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def on_Sample(self, value):
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raise NotImplementedError # :nocov:
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def on_Initial(self, value):
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raise NotImplementedError # :nocov:
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def on_Record(self, value):
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return self(Cat(value.fields.values()))
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class _RHSValueCompiler(_ValueCompiler):
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def __init__(self, signal_slots, sensitivity=None, mode="rhs"):
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self.signal_slots = signal_slots
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self.sensitivity = sensitivity
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self.signal_mode = mode
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def on_Const(self, value):
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return lambda state: value.value
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def on_Signal(self, value):
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if self.sensitivity is not None:
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self.sensitivity.add(value)
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if value not in self.signal_slots:
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# A signal that is neither driven nor a port always remains at its reset state.
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return lambda state: value.reset
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value_slot = self.signal_slots[value]
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if self.signal_mode == "rhs":
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return lambda state: state.curr[value_slot]
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elif self.signal_mode == "lhs":
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return lambda state: state.next[value_slot]
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else:
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raise ValueError # :nocov:
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def on_ClockSignal(self, value):
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raise NotImplementedError # :nocov:
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def on_ResetSignal(self, value):
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raise NotImplementedError # :nocov:
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def on_Operator(self, value):
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shape = value.shape()
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if len(value.operands) == 1:
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arg, = map(self, value.operands)
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if value.op == "~":
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return lambda state: normalize(~arg(state), shape)
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if value.op == "-":
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return lambda state: normalize(-arg(state), shape)
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if value.op == "b":
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return lambda state: normalize(bool(arg(state)), shape)
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if value.op == "r|":
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return lambda state: normalize(arg(state) != 0, shape)
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if value.op == "r&":
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val, = value.operands
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mask = (1 << len(val)) - 1
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return lambda state: normalize(arg(state) == mask, shape)
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if value.op == "r^":
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# Believe it or not, this is the fastest way to compute a sideways XOR in Python.
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return lambda state: normalize(format(arg(state), "b").count("1") % 2, shape)
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elif len(value.operands) == 2:
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lhs, rhs = map(self, value.operands)
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if value.op == "+":
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return lambda state: normalize(lhs(state) + rhs(state), shape)
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if value.op == "-":
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return lambda state: normalize(lhs(state) - rhs(state), shape)
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if value.op == "*":
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return lambda state: normalize(lhs(state) * rhs(state), shape)
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if value.op == "&":
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return lambda state: normalize(lhs(state) & rhs(state), shape)
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if value.op == "|":
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return lambda state: normalize(lhs(state) | rhs(state), shape)
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if value.op == "^":
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return lambda state: normalize(lhs(state) ^ rhs(state), shape)
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if value.op == "<<":
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def sshl(lhs, rhs):
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return lhs << rhs if rhs >= 0 else lhs >> -rhs
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return lambda state: normalize(sshl(lhs(state), rhs(state)), shape)
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if value.op == ">>":
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def sshr(lhs, rhs):
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return lhs >> rhs if rhs >= 0 else lhs << -rhs
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return lambda state: normalize(sshr(lhs(state), rhs(state)), shape)
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if value.op == "==":
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return lambda state: normalize(lhs(state) == rhs(state), shape)
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if value.op == "!=":
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return lambda state: normalize(lhs(state) != rhs(state), shape)
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if value.op == "<":
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return lambda state: normalize(lhs(state) < rhs(state), shape)
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if value.op == "<=":
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return lambda state: normalize(lhs(state) <= rhs(state), shape)
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if value.op == ">":
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return lambda state: normalize(lhs(state) > rhs(state), shape)
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if value.op == ">=":
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return lambda state: normalize(lhs(state) >= rhs(state), shape)
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elif len(value.operands) == 3:
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if value.op == "m":
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sel, val1, val0 = map(self, value.operands)
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return lambda state: val1(state) if sel(state) else val0(state)
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raise NotImplementedError("Operator '{}' not implemented".format(value.op)) # :nocov:
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def on_Slice(self, value):
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shape = value.shape()
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arg = self(value.value)
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shift = value.start
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mask = (1 << (value.end - value.start)) - 1
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return lambda state: normalize((arg(state) >> shift) & mask, shape)
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def on_Part(self, value):
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shape = value.shape()
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arg = self(value.value)
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shift = self(value.offset)
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mask = (1 << value.width) - 1
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stride = value.stride
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return lambda state: normalize((arg(state) >> shift(state) * stride) & mask, shape)
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def on_Cat(self, value):
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shape = value.shape()
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parts = []
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offset = 0
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for opnd in value.parts:
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parts.append((offset, (1 << len(opnd)) - 1, self(opnd)))
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offset += len(opnd)
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def eval(state):
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result = 0
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for offset, mask, opnd in parts:
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result |= (opnd(state) & mask) << offset
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return normalize(result, shape)
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return eval
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def on_Repl(self, value):
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shape = value.shape()
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offset = len(value.value)
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mask = (1 << len(value.value)) - 1
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count = value.count
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opnd = self(value.value)
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def eval(state):
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result = 0
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for _ in range(count):
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result <<= offset
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result |= opnd(state)
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return normalize(result, shape)
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return eval
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def on_ArrayProxy(self, value):
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shape = value.shape()
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elems = list(map(self, value.elems))
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index = self(value.index)
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def eval(state):
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index_value = index(state)
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if index_value >= len(elems):
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index_value = len(elems) - 1
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return normalize(elems[index_value](state), shape)
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return eval
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class _LHSValueCompiler(_ValueCompiler):
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def __init__(self, signal_slots, rhs_compiler):
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self.signal_slots = signal_slots
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self.rhs_compiler = rhs_compiler
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def on_Const(self, value):
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raise TypeError # :nocov:
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def on_Signal(self, value):
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shape = value.shape()
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value_slot = self.signal_slots[value]
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def eval(state, rhs):
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state.set(value_slot, normalize(rhs, shape))
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return eval
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def on_ClockSignal(self, value):
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raise NotImplementedError # :nocov:
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def on_ResetSignal(self, value):
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raise NotImplementedError # :nocov:
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def on_Operator(self, value):
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raise TypeError # :nocov:
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def on_Slice(self, value):
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lhs_r = self.rhs_compiler(value.value)
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lhs_l = self(value.value)
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shift = value.start
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mask = (1 << (value.end - value.start)) - 1
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def eval(state, rhs):
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lhs_value = lhs_r(state)
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lhs_value &= ~(mask << shift)
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lhs_value |= (rhs & mask) << shift
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lhs_l(state, lhs_value)
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return eval
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def on_Part(self, value):
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lhs_r = self.rhs_compiler(value.value)
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lhs_l = self(value.value)
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shift = self.rhs_compiler(value.offset)
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mask = (1 << value.width) - 1
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stride = value.stride
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def eval(state, rhs):
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lhs_value = lhs_r(state)
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shift_value = shift(state) * stride
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lhs_value &= ~(mask << shift_value)
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lhs_value |= (rhs & mask) << shift_value
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lhs_l(state, lhs_value)
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return eval
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def on_Cat(self, value):
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parts = []
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offset = 0
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for opnd in value.parts:
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parts.append((offset, (1 << len(opnd)) - 1, self(opnd)))
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offset += len(opnd)
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def eval(state, rhs):
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for offset, mask, opnd in parts:
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opnd(state, (rhs >> offset) & mask)
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return eval
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def on_Repl(self, value):
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raise TypeError # :nocov:
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def on_ArrayProxy(self, value):
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elems = list(map(self, value.elems))
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index = self.rhs_compiler(value.index)
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def eval(state, rhs):
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index_value = index(state)
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if index_value >= len(elems):
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index_value = len(elems) - 1
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elems[index_value](state, rhs)
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return eval
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class _StatementCompiler(StatementVisitor):
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def __init__(self, signal_slots):
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self.sensitivity = SignalSet()
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self.rrhs_compiler = _RHSValueCompiler(signal_slots, self.sensitivity, mode="rhs")
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self.lrhs_compiler = _RHSValueCompiler(signal_slots, self.sensitivity, mode="lhs")
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self.lhs_compiler = _LHSValueCompiler(signal_slots, self.lrhs_compiler)
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def on_Assign(self, stmt):
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shape = stmt.lhs.shape()
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lhs = self.lhs_compiler(stmt.lhs)
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rhs = self.rrhs_compiler(stmt.rhs)
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def run(state):
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lhs(state, normalize(rhs(state), shape))
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return run
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def on_Assert(self, stmt):
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raise NotImplementedError("Asserts not yet implemented for Simulator backend.") # :nocov:
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def on_Assume(self, stmt):
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pass # :nocov:
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def on_Cover(self, stmt):
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raise NotImplementedError("Covers not yet implemented for Simulator backend.") # :nocov:
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def on_Switch(self, stmt):
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test = self.rrhs_compiler(stmt.test)
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cases = []
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for values, stmts in stmt.cases.items():
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if values == ():
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check = lambda test: True
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else:
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check = lambda test: False
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def make_check(mask, value, prev_check):
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return lambda test: prev_check(test) or test & mask == value
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for value in values:
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if "-" in value:
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mask = "".join("0" if b == "-" else "1" for b in value)
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value = "".join("0" if b == "-" else b for b in value)
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else:
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mask = "1" * len(value)
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mask = int(mask, 2)
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value = int(value, 2)
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check = make_check(mask, value, check)
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cases.append((check, self.on_statements(stmts)))
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def run(state):
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test_value = test(state)
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for check, body in cases:
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if check(test_value):
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body(state)
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return
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return run
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def on_statements(self, stmts):
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stmts = [self.on_statement(stmt) for stmt in stmts]
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def run(state):
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for stmt in stmts:
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stmt(state)
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return run
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class Simulator:
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def __init__(self, fragment, vcd_file=None, gtkw_file=None, traces=()):
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self._fragment = Fragment.get(fragment, platform=None)
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self._signal_slots = SignalDict() # Signal -> int/slot
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self._slot_signals = list() # int/slot -> Signal
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self._domains = list() # [ClockDomain]
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self._clk_edges = dict() # ClockDomain -> int/edge
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self._domain_triggers = list() # int/slot -> ClockDomain
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self._signals = SignalSet() # {Signal}
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self._comb_signals = bitarray() # {Signal}
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self._sync_signals = bitarray() # {Signal}
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self._user_signals = bitarray() # {Signal}
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self._domain_signals = dict() # ClockDomain -> {Signal}
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self._started = False
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self._timestamp = 0.
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self._delta = 0.
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self._epsilon = 1e-10
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self._fastest_clock = self._epsilon
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self._all_clocks = set() # {str/domain}
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self._state = _State()
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self._processes = set() # {process}
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self._process_loc = dict() # process -> str/loc
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self._passive = set() # {process}
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self._suspended = set() # {process}
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self._wait_deadline = dict() # process -> float/timestamp
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self._wait_tick = dict() # process -> str/domain
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self._funclets = list() # int/slot -> set(lambda)
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self._vcd_file = vcd_file
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self._vcd_writer = None
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self._vcd_signals = list() # int/slot -> set(vcd_signal)
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self._vcd_names = list() # int/slot -> str/name
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self._gtkw_file = gtkw_file
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self._traces = traces
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self._run_called = False
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@staticmethod
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def _check_process(process):
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if inspect.isgeneratorfunction(process):
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process = process()
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if not (inspect.isgenerator(process) or inspect.iscoroutine(process)):
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raise TypeError("Cannot add a process '{!r}' because it is not a generator or "
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"a generator function"
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.format(process))
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return process
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def _name_process(self, process):
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if process in self._process_loc:
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return self._process_loc[process]
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else:
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if inspect.isgenerator(process):
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frame = process.gi_frame
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if inspect.iscoroutine(process):
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frame = process.cr_frame
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return "{}:{}".format(inspect.getfile(frame), inspect.getlineno(frame))
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def add_process(self, process):
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process = self._check_process(process)
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self._processes.add(process)
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def add_sync_process(self, process, domain="sync"):
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process = self._check_process(process)
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def sync_process():
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try:
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cmd = None
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while True:
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if cmd is None:
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cmd = Tick(domain)
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result = yield cmd
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self._process_loc[sync_process] = self._name_process(process)
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cmd = process.send(result)
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except StopIteration:
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pass
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sync_process = sync_process()
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self.add_process(sync_process)
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def add_clock(self, period, *, phase=None, domain="sync", if_exists=False):
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if self._fastest_clock == self._epsilon or period < self._fastest_clock:
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self._fastest_clock = period
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if domain in self._all_clocks:
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raise ValueError("Domain '{}' already has a clock driving it"
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.format(domain))
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half_period = period / 2
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if phase is None:
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phase = half_period
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for domain_obj in self._domains:
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if not domain_obj.local and domain_obj.name == domain:
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clk = domain_obj.clk
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break
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else:
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if if_exists:
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return
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else:
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raise ValueError("Domain '{}' is not present in simulation"
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.format(domain))
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def clk_process():
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yield Passive()
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yield Delay(phase)
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while True:
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yield clk.eq(1)
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yield Delay(half_period)
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yield clk.eq(0)
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yield Delay(half_period)
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self.add_process(clk_process)
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self._all_clocks.add(domain)
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def __enter__(self):
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if self._vcd_file:
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self._vcd_writer = VCDWriter(self._vcd_file, timescale="100 ps",
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comment="Generated by nMigen")
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root_fragment = self._fragment.prepare()
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hierarchy = {}
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domains = set()
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def add_fragment(fragment, scope=()):
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hierarchy[fragment] = scope
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domains.update(fragment.domains.values())
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for index, (subfragment, name) in enumerate(fragment.subfragments):
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if name is None:
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add_fragment(subfragment, (*scope, "U{}".format(index)))
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else:
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add_fragment(subfragment, (*scope, name))
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add_fragment(root_fragment, scope=("top",))
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self._domains = list(domains)
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self._clk_edges = {domain: 1 if domain.clk_edge == "pos" else 0 for domain in domains}
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def add_signal(signal):
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if signal not in self._signals:
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self._signals.add(signal)
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|
|
signal_slot = self._state.add(normalize(signal.reset, signal.shape()))
|
|
self._signal_slots[signal] = signal_slot
|
|
self._slot_signals.append(signal)
|
|
|
|
self._comb_signals.append(False)
|
|
self._sync_signals.append(False)
|
|
self._user_signals.append(False)
|
|
for domain in self._domains:
|
|
if domain not in self._domain_signals:
|
|
self._domain_signals[domain] = bitarray()
|
|
self._domain_signals[domain].append(False)
|
|
|
|
self._funclets.append(set())
|
|
|
|
self._domain_triggers.append(None)
|
|
if self._vcd_writer:
|
|
self._vcd_signals.append(set())
|
|
self._vcd_names.append(None)
|
|
|
|
return self._signal_slots[signal]
|
|
|
|
def add_domain_signal(signal, domain):
|
|
signal_slot = add_signal(signal)
|
|
self._domain_triggers[signal_slot] = domain
|
|
|
|
for fragment, fragment_scope in hierarchy.items():
|
|
for signal in fragment.iter_signals():
|
|
add_signal(signal)
|
|
|
|
for domain_name, domain in fragment.domains.items():
|
|
add_domain_signal(domain.clk, domain)
|
|
if domain.rst is not None:
|
|
add_domain_signal(domain.rst, domain)
|
|
|
|
for fragment, fragment_scope in hierarchy.items():
|
|
for signal in fragment.iter_signals():
|
|
if not self._vcd_writer:
|
|
continue
|
|
|
|
signal_slot = self._signal_slots[signal]
|
|
|
|
for i, (subfragment, name) in enumerate(fragment.subfragments):
|
|
if signal in subfragment.ports:
|
|
var_name = "{}_{}".format(name or "U{}".format(i), signal.name)
|
|
break
|
|
else:
|
|
var_name = signal.name
|
|
|
|
if signal.decoder:
|
|
var_type = "string"
|
|
var_size = 1
|
|
var_init = signal.decoder(signal.reset).expandtabs().replace(" ", "_")
|
|
else:
|
|
var_type = "wire"
|
|
var_size = signal.nbits
|
|
var_init = signal.reset
|
|
|
|
suffix = None
|
|
while True:
|
|
try:
|
|
if suffix is None:
|
|
var_name_suffix = var_name
|
|
else:
|
|
var_name_suffix = "{}${}".format(var_name, suffix)
|
|
self._vcd_signals[signal_slot].add(self._vcd_writer.register_var(
|
|
scope=".".join(fragment_scope), name=var_name_suffix,
|
|
var_type=var_type, size=var_size, init=var_init))
|
|
if self._vcd_names[signal_slot] is None:
|
|
self._vcd_names[signal_slot] = \
|
|
".".join(fragment_scope + (var_name_suffix,))
|
|
break
|
|
except KeyError:
|
|
suffix = (suffix or 0) + 1
|
|
|
|
for domain_name, signals in fragment.drivers.items():
|
|
signals_bits = bitarray(len(self._signals))
|
|
signals_bits.setall(False)
|
|
for signal in signals:
|
|
signals_bits[self._signal_slots[signal]] = True
|
|
|
|
if domain_name is None:
|
|
self._comb_signals |= signals_bits
|
|
else:
|
|
self._sync_signals |= signals_bits
|
|
self._domain_signals[fragment.domains[domain_name]] |= signals_bits
|
|
|
|
statements = []
|
|
for domain_name, signals in fragment.drivers.items():
|
|
reset_stmts = []
|
|
hold_stmts = []
|
|
for signal in signals:
|
|
reset_stmts.append(signal.eq(signal.reset))
|
|
hold_stmts .append(signal.eq(signal))
|
|
|
|
if domain_name is None:
|
|
statements += reset_stmts
|
|
else:
|
|
if fragment.domains[domain_name].async_reset:
|
|
statements.append(Switch(fragment.domains[domain_name].rst,
|
|
{0: hold_stmts, 1: reset_stmts}))
|
|
else:
|
|
statements += hold_stmts
|
|
statements += fragment.statements
|
|
|
|
compiler = _StatementCompiler(self._signal_slots)
|
|
funclet = compiler(statements)
|
|
|
|
def add_funclet(signal, funclet):
|
|
if signal in self._signal_slots:
|
|
self._funclets[self._signal_slots[signal]].add(funclet)
|
|
|
|
for signal in compiler.sensitivity:
|
|
add_funclet(signal, funclet)
|
|
for domain in fragment.domains.values():
|
|
add_funclet(domain.clk, funclet)
|
|
if domain.rst is not None:
|
|
add_funclet(domain.rst, funclet)
|
|
|
|
self._user_signals = bitarray(len(self._signals))
|
|
self._user_signals.setall(True)
|
|
self._user_signals &= ~self._comb_signals
|
|
self._user_signals &= ~self._sync_signals
|
|
|
|
return self
|
|
|
|
def _update_dirty_signals(self):
|
|
"""Perform the statement part of IR processes (aka RTLIL case)."""
|
|
# First, for all dirty signals, use sensitivity lists to determine the set of fragments
|
|
# that need their statements to be reevaluated because the signals changed at the previous
|
|
# delta cycle.
|
|
funclets = set()
|
|
for signal_slot in self._state.flush_curr_dirty():
|
|
funclets.update(self._funclets[signal_slot])
|
|
|
|
# Second, compute the values of all signals at the start of the next delta cycle, by
|
|
# running precompiled statements.
|
|
for funclet in funclets:
|
|
funclet(self._state)
|
|
|
|
def _commit_signal(self, signal_slot, domains):
|
|
"""Perform the driver part of IR processes (aka RTLIL sync), for individual signals."""
|
|
# Take the computed value (at the start of this delta cycle) of a signal (that could have
|
|
# come from an IR process that ran earlier, or modified by a simulator process) and update
|
|
# the value for this delta cycle.
|
|
old, new = self._state.commit(signal_slot)
|
|
if old == new:
|
|
return
|
|
|
|
# If the signal is a clock that triggers synchronous logic, record that fact.
|
|
if (self._domain_triggers[signal_slot] is not None and
|
|
self._clk_edges[self._domain_triggers[signal_slot]] == new):
|
|
domains.add(self._domain_triggers[signal_slot])
|
|
|
|
if self._vcd_writer:
|
|
# Finally, dump the new value to the VCD file.
|
|
for vcd_signal in self._vcd_signals[signal_slot]:
|
|
signal = self._slot_signals[signal_slot]
|
|
if signal.decoder:
|
|
var_value = signal.decoder(new).expandtabs().replace(" ", "_")
|
|
else:
|
|
var_value = new
|
|
vcd_timestamp = (self._timestamp + self._delta) / self._epsilon
|
|
self._vcd_writer.change(vcd_signal, vcd_timestamp, var_value)
|
|
|
|
def _commit_comb_signals(self, domains):
|
|
"""Perform the comb part of IR processes (aka RTLIL always)."""
|
|
# Take the computed value (at the start of this delta cycle) of every comb signal and
|
|
# update the value for this delta cycle.
|
|
for signal_slot in self._state.iter_next_dirty():
|
|
if self._comb_signals[signal_slot]:
|
|
self._commit_signal(signal_slot, domains)
|
|
|
|
def _commit_sync_signals(self, domains):
|
|
"""Perform the sync part of IR processes (aka RTLIL posedge)."""
|
|
# At entry, `domains` contains a set of every simultaneously triggered sync update.
|
|
while domains:
|
|
# Advance the timeline a bit (purely for observational purposes) and commit all of them
|
|
# at the same timestamp.
|
|
self._delta += self._epsilon
|
|
curr_domains, domains = domains, set()
|
|
|
|
while curr_domains:
|
|
domain = curr_domains.pop()
|
|
|
|
# Wake up any simulator processes that wait for a domain tick.
|
|
for process, wait_domain_name in list(self._wait_tick.items()):
|
|
if domain.name == wait_domain_name:
|
|
del self._wait_tick[process]
|
|
self._suspended.remove(process)
|
|
|
|
# Immediately run the process. It is important that this happens here,
|
|
# and not on the next step, when all the processes will run anyway,
|
|
# because Tick() simulates an edge triggered process. Like DFFs that latch
|
|
# a value from the previous clock cycle, simulator processes observe signal
|
|
# values from the previous clock cycle on a tick, too.
|
|
self._run_process(process)
|
|
|
|
# Take the computed value (at the start of this delta cycle) of every sync signal
|
|
# in this domain and update the value for this delta cycle. This can trigger more
|
|
# synchronous logic, so record that.
|
|
for signal_slot in self._state.iter_next_dirty():
|
|
if self._domain_signals[domain][signal_slot]:
|
|
self._commit_signal(signal_slot, domains)
|
|
|
|
# Unless handling synchronous logic above has triggered more synchronous logic (which
|
|
# can happen e.g. if a domain is clocked off a clock divisor in fabric), we're done.
|
|
# Otherwise, do one more round of updates.
|
|
|
|
def _run_process(self, process):
|
|
try:
|
|
cmd = process.send(None)
|
|
while True:
|
|
if type(cmd) is Delay:
|
|
if cmd.interval is None:
|
|
interval = self._epsilon
|
|
else:
|
|
interval = cmd.interval
|
|
self._wait_deadline[process] = self._timestamp + interval
|
|
self._suspended.add(process)
|
|
break
|
|
|
|
elif type(cmd) is Tick:
|
|
self._wait_tick[process] = cmd.domain
|
|
self._suspended.add(process)
|
|
break
|
|
|
|
elif type(cmd) is Passive:
|
|
self._passive.add(process)
|
|
|
|
elif type(cmd) is Assign:
|
|
lhs_signals = cmd.lhs._lhs_signals()
|
|
for signal in lhs_signals:
|
|
if not signal in self._signals:
|
|
raise ValueError("Process '{}' sent a request to set signal '{!r}', "
|
|
"which is not a part of simulation"
|
|
.format(self._name_process(process), signal))
|
|
signal_slot = self._signal_slots[signal]
|
|
if self._comb_signals[signal_slot]:
|
|
raise ValueError("Process '{}' sent a request to set signal '{!r}', "
|
|
"which is a part of combinatorial assignment in "
|
|
"simulation"
|
|
.format(self._name_process(process), signal))
|
|
|
|
if type(cmd.lhs) is Signal and type(cmd.rhs) is Const:
|
|
# Fast path.
|
|
self._state.set(self._signal_slots[cmd.lhs],
|
|
normalize(cmd.rhs.value, cmd.lhs.shape()))
|
|
else:
|
|
compiler = _StatementCompiler(self._signal_slots)
|
|
funclet = compiler(cmd)
|
|
funclet(self._state)
|
|
|
|
domains = set()
|
|
for signal in lhs_signals:
|
|
self._commit_signal(self._signal_slots[signal], domains)
|
|
self._commit_sync_signals(domains)
|
|
|
|
elif type(cmd) is Signal:
|
|
# Fast path.
|
|
cmd = process.send(self._state.curr[self._signal_slots[cmd]])
|
|
continue
|
|
|
|
elif isinstance(cmd, Value):
|
|
compiler = _RHSValueCompiler(self._signal_slots)
|
|
funclet = compiler(cmd)
|
|
cmd = process.send(funclet(self._state))
|
|
continue
|
|
|
|
else:
|
|
raise TypeError("Received unsupported command '{!r}' from process '{}'"
|
|
.format(cmd, self._name_process(process)))
|
|
|
|
cmd = process.send(None)
|
|
|
|
except StopIteration:
|
|
self._processes.remove(process)
|
|
self._passive.discard(process)
|
|
|
|
except Exception as e:
|
|
process.throw(e)
|
|
|
|
def step(self, run_passive=False):
|
|
# Are there any delta cycles we should run?
|
|
if self._state.curr_dirty.any():
|
|
# We might run some delta cycles, and we have simulator processes waiting on
|
|
# a deadline. Take care to not exceed the closest deadline.
|
|
if self._wait_deadline and \
|
|
(self._timestamp + self._delta) >= min(self._wait_deadline.values()):
|
|
# Oops, we blew the deadline. We *could* run the processes now, but this is
|
|
# virtually certainly a logic loop and a design bug, so bail out instead.d
|
|
raise DeadlineError("Delta cycles exceeded process deadline; combinatorial loop?")
|
|
|
|
domains = set()
|
|
while self._state.curr_dirty.any():
|
|
self._update_dirty_signals()
|
|
self._commit_comb_signals(domains)
|
|
self._commit_sync_signals(domains)
|
|
return True
|
|
|
|
# Are there any processes that haven't had a chance to run yet?
|
|
if len(self._processes) > len(self._suspended):
|
|
# Schedule an arbitrary one.
|
|
process = (self._processes - set(self._suspended)).pop()
|
|
self._run_process(process)
|
|
return True
|
|
|
|
# All processes are suspended. Are any of them active?
|
|
if len(self._processes) > len(self._passive) or run_passive:
|
|
# Are any of them suspended before a deadline?
|
|
if self._wait_deadline:
|
|
# Schedule the one with the lowest deadline.
|
|
process, deadline = min(self._wait_deadline.items(), key=lambda x: x[1])
|
|
del self._wait_deadline[process]
|
|
self._suspended.remove(process)
|
|
self._timestamp = deadline
|
|
self._delta = 0.
|
|
self._run_process(process)
|
|
return True
|
|
|
|
# No processes, or all processes are passive. Nothing to do!
|
|
return False
|
|
|
|
def run(self):
|
|
self._run_called = True
|
|
|
|
while self.step():
|
|
pass
|
|
|
|
def run_until(self, deadline, run_passive=False):
|
|
self._run_called = True
|
|
|
|
while self._timestamp < deadline:
|
|
if not self.step(run_passive):
|
|
return False
|
|
|
|
return True
|
|
|
|
def __exit__(self, *args):
|
|
if not self._run_called:
|
|
warnings.warn("Simulation created, but not run", UserWarning)
|
|
|
|
if self._vcd_writer:
|
|
vcd_timestamp = (self._timestamp + self._delta) / self._epsilon
|
|
self._vcd_writer.close(vcd_timestamp)
|
|
|
|
if self._vcd_file and self._gtkw_file:
|
|
gtkw_save = GTKWSave(self._gtkw_file)
|
|
if hasattr(self._vcd_file, "name"):
|
|
gtkw_save.dumpfile(self._vcd_file.name)
|
|
if hasattr(self._vcd_file, "tell"):
|
|
gtkw_save.dumpfile_size(self._vcd_file.tell())
|
|
|
|
gtkw_save.treeopen("top")
|
|
gtkw_save.zoom_markers(math.log(self._epsilon / self._fastest_clock) - 14)
|
|
|
|
def add_trace(signal, **kwargs):
|
|
signal_slot = self._signal_slots[signal]
|
|
if self._vcd_names[signal_slot] is not None:
|
|
if len(signal) > 1 and not signal.decoder:
|
|
suffix = "[{}:0]".format(len(signal) - 1)
|
|
else:
|
|
suffix = ""
|
|
gtkw_save.trace(self._vcd_names[signal_slot] + suffix, **kwargs)
|
|
|
|
for domain in self._domains:
|
|
with gtkw_save.group("d.{}".format(domain.name)):
|
|
if domain.rst is not None:
|
|
add_trace(domain.rst)
|
|
add_trace(domain.clk)
|
|
|
|
for signal in self._traces:
|
|
add_trace(signal)
|
|
|
|
if self._vcd_file:
|
|
self._vcd_file.close()
|
|
if self._gtkw_file:
|
|
self._gtkw_file.close()
|