amaranth/examples/basic
whitequark b65e11f38f sim: split into base, core, and engines.
Before this commit, each simulation engine (which is only pysim at
the moment, but also cxxsim soon) was a subclass of SimulatorCore,
and every simulation engine module would essentially duplicate
the complete structure of a simulator, with code partially shared.

This was a really bad idea: it was inconvenient to use, with
downstream code having to branch between e.g. PySettle and CxxSettle;
it had no well-defined external interface; it had multiple virtually
identical entry points; and it had no separation between simulation
algorithms and glue code.

This commit completely rearranges simulation code.
  1. sim._base defines internal simulation interfaces. The clarity of
     these internal interfaces is important because simulation
     engines mix and match components to provide a consistent API
     regardless of the chosen engine.
  2. sim.core defines the external simulation interface: the commands
     and the simulator facade. The facade provides a single entry
     point and, when possible, validates or lowers user input.
     It also imports built-in simulation engines by their symbolic
     name, avoiding eager imports of pyvcd or ctypes.
  3. sim.xxxsim (currently, only sim.pysim) defines the simulator
     implementation: time and state management, process scheduling,
     and waveform dumping.

The new simulator structure has none of the downsides of the old one.

See #324.
2020-08-27 11:52:31 +00:00
..
alu.py examples: reorganize into examples/basic and examples/board. 2019-06-03 16:17:37 +00:00
alu_hier.py examples: reorganize into examples/basic and examples/board. 2019-06-03 16:17:37 +00:00
arst.py test: generate examples to verilog as part of unit tests. 2019-07-08 10:12:26 +00:00
cdc.py lib.cdc: MultiReg→FFSynchronizer. 2019-09-23 14:18:45 +00:00
ctr.py examples: reorganize into examples/basic and examples/board. 2019-06-03 16:17:37 +00:00
ctr_en.py sim: split into base, core, and engines. 2020-08-27 11:52:31 +00:00
fsm.py hdl.ast: deprecate Signal.{range,enum}. 2019-10-11 13:07:42 +00:00
gpio.py examples: reorganize into examples/basic and examples/board. 2019-06-03 16:17:37 +00:00
inst.py examples: reorganize into examples/basic and examples/board. 2019-06-03 16:17:37 +00:00
mem.py examples: reorganize into examples/basic and examples/board. 2019-06-03 16:17:37 +00:00
pmux.py examples: reorganize into examples/basic and examples/board. 2019-06-03 16:17:37 +00:00
por.py hdl.ast: deprecate Signal.{range,enum}. 2019-10-11 13:07:42 +00:00
sel.py back.rtlil: fix lowering of Part() on LHS to account for stride. 2019-10-26 01:52:34 +00:00
uart.py hdl.ast: actually remove simulator commands. 2019-12-02 02:24:24 +00:00