whitequark 7aedb3e770 back.rtlil: lower maximum accepted wire size. ... In practice wires of just 100000 bits sometimes have unacceptable performance with Yosys, so stick to Verilog's minimum limit of 65536 bits.		2020-07-22 14:43:44 +00:00
..
__init__.py	Initial commit.	2018-12-12 03:18:44 +00:00
cxxrtl.py	_yosys→_toolchain.yosys	2020-07-02 18:26:08 +00:00
pysim.py	back.pysim→sim.pysim; split into more manageable parts.	2020-07-08 12:49:38 +00:00
rtlil.py	back.rtlil: lower maximum accepted wire size.	2020-07-22 14:43:44 +00:00
verilog.py	_yosys→_toolchain.yosys	2020-07-02 18:26:08 +00:00