whitequark 851ed06769 ClockDomain.{rst→reset}, for consistency with ResetInserter. ... nmigen.compat.ClockDomain would alias this, for Migen compatibility.		2018-12-12 09:49:02 +00:00
..
__init__.py	Initial commit.	2018-12-12 03:18:44 +00:00
rtlil.py	ClockDomain.{rst→reset}, for consistency with ResetInserter.	2018-12-12 09:49:02 +00:00
verilog.py	Initial commit.	2018-12-12 03:18:44 +00:00