whitequark 882fddfa96 back.pysim: emit toplevel inputs in VCD files as well. ... Before this commit, only signals driven from fragments (in practice, everything except toplevel inputs) would get written to a VCD file. Not having toplevel inputs in the dump made debugging ~impossible. After this commit, all signals the fragment refers to get written to a VCD file. (More specifically, all signals the compiler assigns an index to, i.e. signals the generated code reads or writes.) Fixes #280.		2020-02-06 17:19:47 +00:00
..
__init__.py	Initial commit.	2018-12-12 03:18:44 +00:00
pysim.py	back.pysim: emit toplevel inputs in VCD files as well.	2020-02-06 17:19:47 +00:00
rtlil.py	hdl.mem: add synthesis attribute support.	2020-02-06 14:53:16 +00:00
verilog.py	back.verilog: remove $verilog_initial_trigger after proc_prune.	2019-10-28 10:11:41 +00:00