Marcelina Kościelnicka 8c4a15ab92 hdl.mem: lower Memory directly to $mem_v2 RTLIL cell. ... The design decision of using split memory ports in the internal representation (copied from Yosys) was misguided and caused no end of misery. Remove any uses of `$memrd`/`$memwr` and lower memories directly to a combined memory cell, currently the RTLIL one.		2023-09-03 03:27:51 +00:00
..
_code	Rename nMigen to Amaranth HDL.	2021-12-10 10:34:13 +00:00
_images	Add (heavily work in progress) documentation.	2020-06-30 22:21:16 +00:00
_static	docs: use sphinxcontrib-platformpicker.	2020-07-05 23:39:47 +00:00
platform	Implement RFC 18: Reorganize vendor platforms	2023-09-01 00:37:48 +00:00
stdlib	docs/enum: emphasize that shape= is optional.	2023-08-31 02:16:26 +00:00
.gitignore	Add (heavily work in progress) documentation.	2020-06-30 22:21:16 +00:00
changes.rst	hdl.mem: lower Memory directly to $mem_v2 RTLIL cell.	2023-09-03 03:27:51 +00:00
conf.py	lib.enum: add Enum wrappers that allow specifying shape.	2023-02-28 13:00:41 +00:00
contrib.rst	docs/contrib: fix typo.	2023-08-16 09:39:59 +00:00
cover.rst	CI: publish documentation at https://amaranth-lang.org/docs/amaranth/	2021-12-16 17:51:53 +00:00
index.rst	docs/contrib: begin writing a contribution guide.	2023-07-24 13:46:48 +00:00
install.rst	Drop support for Python 3.7.	2023-06-28 14:50:30 +00:00
intro.rst	Rename nMigen to Amaranth HDL.	2021-12-10 10:34:13 +00:00
lang.rst	docs/lang: capture and verify an expected warning in doctest.	2023-07-24 13:46:48 +00:00
platform.rst	vendor.gowin: new platform.	2023-08-08 12:38:36 +00:00
start.rst	docs: fix download link in start.rst.	2021-12-11 06:32:32 +00:00
stdlib.rst	Implement RFC 6: CRC Generator	2023-06-29 02:42:47 +00:00
tutorial.rst	docs: Minor typo in tutorial.rst	2023-08-10 18:12:07 +00:00