317 lines
7.8 KiB
Python
317 lines
7.8 KiB
Python
from ..hdl.ast import *
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from ..hdl.cd import *
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from ..hdl.ir import *
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from ..hdl.xfrm import *
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from .tools import *
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class DomainRenamerTestCase(FHDLTestCase):
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def setUp(self):
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self.s1 = Signal()
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self.s2 = Signal()
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self.s3 = Signal()
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self.s4 = Signal()
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self.s5 = Signal()
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self.c1 = Signal()
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def test_rename_signals(self):
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f = Fragment()
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f.add_statements(
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self.s1.eq(ClockSignal()),
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ResetSignal().eq(self.s2),
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self.s3.eq(0),
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self.s4.eq(ClockSignal("other")),
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self.s5.eq(ResetSignal("other")),
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)
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f.add_driver(self.s1, None)
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f.add_driver(self.s2, None)
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f.add_driver(self.s3, "sync")
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f = DomainRenamer("pix")(f)
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self.assertRepr(f.statements, """
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(
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(eq (sig s1) (clk pix))
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(eq (rst pix) (sig s2))
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(eq (sig s3) (const 1'd0))
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(eq (sig s4) (clk other))
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(eq (sig s5) (rst other))
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)
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""")
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self.assertEqual(f.drivers, {
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None: SignalSet((self.s1, self.s2)),
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"pix": SignalSet((self.s3,)),
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})
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def test_rename_multi(self):
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f = Fragment()
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f.add_statements(
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self.s1.eq(ClockSignal()),
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self.s2.eq(ResetSignal("other")),
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)
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f = DomainRenamer({"sync": "pix", "other": "pix2"})(f)
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self.assertRepr(f.statements, """
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(
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(eq (sig s1) (clk pix))
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(eq (sig s2) (rst pix2))
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)
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""")
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def test_rename_cd(self):
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cd_sync = ClockDomain()
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cd_pix = ClockDomain()
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f = Fragment()
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f.add_domains(cd_sync, cd_pix)
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f = DomainRenamer("ext")(f)
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self.assertEqual(cd_sync.name, "ext")
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self.assertEqual(f.domains, {
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"ext": cd_sync,
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"pix": cd_pix,
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})
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def test_rename_cd_subfragment(self):
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cd_sync = ClockDomain()
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cd_pix = ClockDomain()
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f1 = Fragment()
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f1.add_domains(cd_sync, cd_pix)
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f2 = Fragment()
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f2.add_domains(cd_sync)
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f1.add_subfragment(f2)
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f1 = DomainRenamer("ext")(f1)
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self.assertEqual(cd_sync.name, "ext")
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self.assertEqual(f1.domains, {
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"ext": cd_sync,
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"pix": cd_pix,
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})
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class DomainLowererTestCase(FHDLTestCase):
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def setUp(self):
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self.s = Signal()
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def test_lower_clk(self):
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sync = ClockDomain()
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f = Fragment()
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f.add_statements(
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self.s.eq(ClockSignal("sync"))
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)
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f = DomainLowerer({"sync": sync})(f)
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self.assertRepr(f.statements, """
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(
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(eq (sig s) (sig clk))
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)
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""")
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def test_lower_rst(self):
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sync = ClockDomain()
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f = Fragment()
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f.add_statements(
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self.s.eq(ResetSignal("sync"))
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)
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f = DomainLowerer({"sync": sync})(f)
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self.assertRepr(f.statements, """
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(
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(eq (sig s) (sig rst))
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)
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""")
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def test_lower_rst_reset_less(self):
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sync = ClockDomain(reset_less=True)
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f = Fragment()
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f.add_statements(
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self.s.eq(ResetSignal("sync", allow_reset_less=True))
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)
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f = DomainLowerer({"sync": sync})(f)
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self.assertRepr(f.statements, """
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(
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(eq (sig s) (const 1'd0))
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)
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""")
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def test_lower_wrong_domain(self):
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sync = ClockDomain()
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f = Fragment()
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f.add_statements(
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self.s.eq(ClockSignal("xxx"))
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)
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with self.assertRaises(DomainError,
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msg="Signal (clk xxx) refers to nonexistent domain 'xxx'"):
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DomainLowerer({"sync": sync})(f)
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def test_lower_wrong_reset_less_domain(self):
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sync = ClockDomain(reset_less=True)
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f = Fragment()
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f.add_statements(
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self.s.eq(ResetSignal("sync"))
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)
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with self.assertRaises(DomainError,
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msg="Signal (rst sync) refers to reset of reset-less domain 'sync'"):
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DomainLowerer({"sync": sync})(f)
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class ResetInserterTestCase(FHDLTestCase):
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def setUp(self):
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self.s1 = Signal()
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self.s2 = Signal(reset=1)
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self.s3 = Signal(reset=1, reset_less=True)
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self.c1 = Signal()
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def test_reset_default(self):
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f = Fragment()
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f.add_statements(
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self.s1.eq(1)
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)
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f.add_driver(self.s1, "sync")
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f = ResetInserter(self.c1)(f)
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self.assertRepr(f.statements, """
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(
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(eq (sig s1) (const 1'd1))
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(switch (sig c1)
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(case 1 (eq (sig s1) (const 1'd0)))
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)
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)
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""")
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def test_reset_cd(self):
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f = Fragment()
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f.add_statements(
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self.s1.eq(1),
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self.s2.eq(0),
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)
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f.add_domains(ClockDomain("sync"))
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f.add_driver(self.s1, "sync")
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f.add_driver(self.s2, "pix")
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f = ResetInserter({"pix": self.c1})(f)
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self.assertRepr(f.statements, """
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(
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(eq (sig s1) (const 1'd1))
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(eq (sig s2) (const 1'd0))
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(switch (sig c1)
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(case 1 (eq (sig s2) (const 1'd1)))
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)
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)
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""")
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def test_reset_value(self):
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f = Fragment()
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f.add_statements(
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self.s2.eq(0)
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)
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f.add_driver(self.s2, "sync")
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f = ResetInserter(self.c1)(f)
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self.assertRepr(f.statements, """
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(
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(eq (sig s2) (const 1'd0))
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(switch (sig c1)
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(case 1 (eq (sig s2) (const 1'd1)))
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)
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)
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""")
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def test_reset_less(self):
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f = Fragment()
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f.add_statements(
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self.s3.eq(0)
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)
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f.add_driver(self.s3, "sync")
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f = ResetInserter(self.c1)(f)
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self.assertRepr(f.statements, """
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(
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(eq (sig s3) (const 1'd0))
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(switch (sig c1)
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(case 1 )
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)
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)
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""")
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class CEInserterTestCase(FHDLTestCase):
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def setUp(self):
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self.s1 = Signal()
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self.s2 = Signal()
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self.s3 = Signal()
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self.c1 = Signal()
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def test_ce_default(self):
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f = Fragment()
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f.add_statements(
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self.s1.eq(1)
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)
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f.add_driver(self.s1, "sync")
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f = CEInserter(self.c1)(f)
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self.assertRepr(f.statements, """
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(
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(eq (sig s1) (const 1'd1))
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(switch (sig c1)
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(case 0 (eq (sig s1) (sig s1)))
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)
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)
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""")
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def test_ce_cd(self):
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f = Fragment()
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f.add_statements(
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self.s1.eq(1),
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self.s2.eq(0),
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)
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f.add_driver(self.s1, "sync")
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f.add_driver(self.s2, "pix")
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f = CEInserter({"pix": self.c1})(f)
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self.assertRepr(f.statements, """
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(
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(eq (sig s1) (const 1'd1))
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(eq (sig s2) (const 1'd0))
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(switch (sig c1)
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(case 0 (eq (sig s2) (sig s2)))
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)
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)
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""")
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def test_ce_subfragment(self):
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f1 = Fragment()
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f1.add_statements(
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self.s1.eq(1)
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)
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f1.add_driver(self.s1, "sync")
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f2 = Fragment()
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f2.add_statements(
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self.s2.eq(1)
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)
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f2.add_driver(self.s2, "sync")
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f1.add_subfragment(f2)
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f1 = CEInserter(self.c1)(f1)
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(f2, _), = f1.subfragments
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self.assertRepr(f1.statements, """
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(
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(eq (sig s1) (const 1'd1))
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(switch (sig c1)
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(case 0 (eq (sig s1) (sig s1)))
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)
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)
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""")
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self.assertRepr(f2.statements, """
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(
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(eq (sig s2) (const 1'd1))
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(switch (sig c1)
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(case 0 (eq (sig s2) (sig s2)))
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)
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)
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""")
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