whitequark 90f1503c91 fhdl.ir: record port direction explicitly. ... No point in recalculating this in the backend when writing RTLIL or Verilog port directions.		2018-12-13 13:12:31 +00:00
..
__init__.py	Initial commit.	2018-12-12 03:18:44 +00:00
rtlil.py	fhdl.ir: record port direction explicitly.	2018-12-13 13:12:31 +00:00
verilog.py	compat.genlib.fsm: import/wrap Migen code.	2018-12-13 12:41:19 +00:00