
No point in recalculating this in the backend when writing RTLIL or Verilog port directions.
170 lines
7 KiB
Python
170 lines
7 KiB
Python
from collections import defaultdict, OrderedDict
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from ..tools import *
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from .ast import *
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from .cd import *
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__all__ = ["Fragment", "DomainError"]
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class DomainError(Exception):
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pass
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class Fragment:
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def __init__(self):
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self.ports = ValueDict()
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self.drivers = OrderedDict()
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self.statements = []
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self.domains = OrderedDict()
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self.subfragments = []
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def add_ports(self, *ports, kind):
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assert kind in ("i", "o", "io")
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for port in flatten(ports):
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self.ports[port] = kind
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def iter_ports(self):
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yield from self.ports.keys()
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def drive(self, signal, domain=None):
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if domain not in self.drivers:
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self.drivers[domain] = ValueSet()
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self.drivers[domain].add(signal)
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def iter_drivers(self):
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for domain, signals in self.drivers.items():
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for signal in signals:
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yield domain, signal
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def iter_comb(self):
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yield from self.drivers[None]
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def iter_sync(self):
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for domain, signals in self.drivers.items():
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if domain is None:
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continue
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for signal in signals:
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yield domain, signal
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def add_domains(self, *domains):
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for domain in domains:
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assert isinstance(domain, ClockDomain)
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assert domain.name not in self.domains
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self.domains[domain.name] = domain
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def iter_domains(self):
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yield from self.domains
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def add_statements(self, *stmts):
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self.statements += Statement.wrap(stmts)
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def add_subfragment(self, subfragment, name=None):
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assert isinstance(subfragment, Fragment)
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self.subfragments.append((subfragment, name))
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def _propagate_domains_up(self, hierarchy=("top",)):
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from .xfrm import DomainRenamer
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domain_subfrags = defaultdict(lambda: set())
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# For each domain defined by a subfragment, determine which subfragments define it.
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for i, (subfrag, name) in enumerate(self.subfragments):
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# First, recurse into subfragments and let them propagate domains up as well.
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hier_name = name
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if hier_name is None:
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hier_name = "<unnamed #{}>".format(i)
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subfrag._propagate_domains_up(hierarchy + (hier_name,))
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# Second, classify subfragments by domains they define.
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for domain in subfrag.iter_domains():
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domain_subfrags[domain].add((subfrag, name, i))
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# For each domain defined by more than one subfragment, rename the domain in each
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# of the subfragments such that they no longer conflict.
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for domain, subfrags in domain_subfrags.items():
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if len(subfrags) == 1:
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continue
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names = [n for f, n, i in subfrags]
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if not all(names):
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names = sorted("<unnamed #{}>".format(i) if n is None else "'{}'".format(n)
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for f, n, i in subfrags)
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raise DomainError("Domain '{}' is defined by subfragments {} of fragment '{}'; "
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"it is necessary to either rename subfragment domains "
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"explicitly, or give names to subfragments"
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.format(domain, ", ".join(names), ".".join(hierarchy)))
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if len(names) != len(set(names)):
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names = sorted("#{}".format(i) for f, n, i in subfrags)
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raise DomainError("Domain '{}' is defined by subfragments {} of fragment '{}', "
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"some of which have identical names; it is necessary to either "
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"rename subfragment domains explicitly, or give distinct names "
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"to subfragments"
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.format(domain, ", ".join(names), ".".join(hierarchy)))
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for subfrag, name, i in subfrags:
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self.subfragments[i] = \
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(DomainRenamer({domain: "{}_{}".format(name, domain)})(subfrag), name)
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# Finally, collect the (now unique) subfragment domains, and merge them into our domains.
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for subfrag, name in self.subfragments:
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for domain in subfrag.iter_domains():
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self.add_domains(subfrag.domains[domain])
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def _propagate_domains_down(self):
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# For each domain defined in this fragment, ensure it also exists in all subfragments.
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for subfrag, name in self.subfragments:
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for domain in self.iter_domains():
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if domain in subfrag.domains:
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assert self.domains[domain] is subfrag.domains[domain]
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else:
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subfrag.add_domains(self.domains[domain])
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subfrag._propagate_domains_down()
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def _propagate_domains(self, ensure_sync_exists=False):
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self._propagate_domains_up()
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if ensure_sync_exists and not self.domains:
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self.add_domains(ClockDomain("sync"))
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self._propagate_domains_down()
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def _propagate_ports(self, ports):
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# Collect all signals we're driving (on LHS of statements), and signals we're using
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# (on RHS of statements, or in clock domains).
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self_driven = union(s._lhs_signals() for s in self.statements) or ValueSet()
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self_used = union(s._rhs_signals() for s in self.statements) or ValueSet()
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for domain, _ in self.iter_sync():
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cd = self.domains[domain]
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self_used.add(cd.clk)
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if cd.rst is not None:
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self_used.add(cd.rst)
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# Our input ports are all the signals we're using but not driving. This is an over-
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# approximation: some of these signals may be driven by our subfragments.
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ins = self_used - self_driven
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# Our output ports are all the signals we're asked to provide that we're driving. This is
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# an underapproximation: some of these signals may be driven by subfragments.
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outs = ports & self_driven
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# Go through subfragments and refine our approximation for ports.
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for subfrag, name in self.subfragments:
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# Always ask subfragments to provide all signals we're using and signals we're asked
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# to provide. If the subfragment is not driving it, it will silently ignore it.
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sub_ins, sub_outs = subfrag._propagate_ports(ports=self_used | ports)
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# Refine the input port approximation: if a subfragment is driving a signal,
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# it is definitely not our input. But, if a subfragment requires a signal as an input,
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# and we aren't driving it, it has to be our input as well.
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ins -= sub_outs
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ins |= sub_ins - self_driven
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# Refine the output port approximation: if a subfragment is driving a signal,
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# and we're asked to provide it, we can provide it now.
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outs |= ports & sub_outs
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# We've computed the precise set of input and output ports.
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self.add_ports(ins, kind="i")
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self.add_ports(outs, kind="o")
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return ins, outs
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