whitequark 90f1503c91 fhdl.ir: record port direction explicitly. ... No point in recalculating this in the backend when writing RTLIL or Verilog port directions.		2018-12-13 13:12:31 +00:00
..
__init__.py	fhdl.ast: add tests for most logic.	2018-12-13 02:06:55 +00:00
test_fhdl_cd.py	fhdl.cd: add tests.	2018-12-13 09:19:16 +00:00
test_fhdl_dsl.py	fhdl.ir: implement clock domain propagation.	2018-12-13 11:01:03 +00:00
test_fhdl_ir.py	fhdl.ir: record port direction explicitly.	2018-12-13 13:12:31 +00:00
test_fhdl_value.py	fhdl.cd: add tests.	2018-12-13 09:19:16 +00:00
test_fhdl_xfrm.py	fhdl.ir: implement clock domain propagation.	2018-12-13 11:01:03 +00:00
tools.py	fhdl.ir: implement clock domain propagation.	2018-12-13 11:01:03 +00:00