whitequark 4e32f6b8de back.verilog: detect undriven public wires using Yosys. ... This should never happen, and is certainly a logic bug in nMigen.		2018-12-13 04:59:48 +00:00
..
__init__.py	Initial commit.	2018-12-12 03:18:44 +00:00
rtlil.py	back.rtlil: fix swapped operands in sync assign.	2018-12-13 04:34:22 +00:00
verilog.py	back.verilog: detect undriven public wires using Yosys.	2018-12-13 04:59:48 +00:00