whitequark 935bf2d8cf back.rtlil: rename \sig$next to $next$sig. ... These used to serve a useful purpose being public, back when the RTLIL backend was immature. Not anymore; now they merely clutter up views in gtkwave and so on.		2019-01-16 14:51:20 +00:00
..
__init__.py	Initial commit.	2018-12-12 03:18:44 +00:00
pysim.py	hdl.xfrm: Add on_AnyConst and on_AnySeq abstract methods for ValueVisitor and children.	2019-01-15 22:52:45 +00:00
rtlil.py	back.rtlil: rename \sig$next to $next$sig.	2019-01-16 14:51:20 +00:00
verilog.py	back.verilog: better error message if Yosys is not found.	2019-01-13 08:10:23 +00:00