79adbed313
At the moment there are two issues with assignment of names in pysim: 1. Names are not deduplicated. It is possible (and frequent) for names to be included twice in VCD output. 2. Names are different compared to what is emitted in RTLIL, Verilog, or CXXRTL output. This commit fixes issue (1), and issue (2) will be fixed by the new IR.
905 lines
27 KiB
Python
905 lines
27 KiB
Python
# amaranth: UnusedElaboratable=no
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from collections import OrderedDict
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from amaranth.hdl.ast import *
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from amaranth.hdl.cd import *
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from amaranth.hdl.ir import *
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from amaranth.hdl.mem import *
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from .utils import *
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class ElaboratesToNone(Elaboratable):
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def elaborate(self, platform):
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return
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class ElaboratesToSelf(Elaboratable):
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def elaborate(self, platform):
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return self
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class FragmentGetTestCase(FHDLTestCase):
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def test_get_wrong_none(self):
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with self.assertRaisesRegex(AttributeError,
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r"^Object None cannot be elaborated$"):
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Fragment.get(None, platform=None)
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with self.assertWarnsRegex(UserWarning,
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r"^\.elaborate\(\) returned None; missing return statement\?$"):
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with self.assertRaisesRegex(AttributeError,
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r"^Object None cannot be elaborated$"):
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Fragment.get(ElaboratesToNone(), platform=None)
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def test_get_wrong_self(self):
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with self.assertRaisesRegex(RecursionError,
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r"^Object <.+?ElaboratesToSelf.+?> elaborates to itself$"):
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Fragment.get(ElaboratesToSelf(), platform=None)
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class FragmentGeneratedTestCase(FHDLTestCase):
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def test_find_subfragment(self):
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f1 = Fragment()
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f2 = Fragment()
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f1.add_subfragment(f2, "f2")
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self.assertEqual(f1.find_subfragment(0), f2)
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self.assertEqual(f1.find_subfragment("f2"), f2)
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def test_find_subfragment_wrong(self):
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f1 = Fragment()
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f2 = Fragment()
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f1.add_subfragment(f2, "f2")
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with self.assertRaisesRegex(NameError,
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r"^No subfragment at index #1$"):
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f1.find_subfragment(1)
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with self.assertRaisesRegex(NameError,
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r"^No subfragment with name 'fx'$"):
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f1.find_subfragment("fx")
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def test_find_generated(self):
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f1 = Fragment()
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f2 = Fragment()
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f2.generated["sig"] = sig = Signal()
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f1.add_subfragment(f2, "f2")
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self.assertEqual(SignalKey(f1.find_generated("f2", "sig")),
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SignalKey(sig))
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class FragmentDriversTestCase(FHDLTestCase):
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def test_empty(self):
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f = Fragment()
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self.assertEqual(list(f.iter_comb()), [])
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self.assertEqual(list(f.iter_sync()), [])
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class FragmentPortsTestCase(FHDLTestCase):
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def setUp(self):
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self.s1 = Signal()
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self.s2 = Signal()
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self.s3 = Signal()
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self.c1 = Signal()
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self.c2 = Signal()
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self.c3 = Signal()
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def test_empty(self):
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f = Fragment()
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self.assertEqual(list(f.iter_ports()), [])
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f._propagate_ports(ports=(), all_undef_as_ports=True)
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self.assertEqual(f.ports, SignalDict([]))
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def test_iter_signals(self):
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f = Fragment()
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f.add_ports(self.s1, self.s2, dir="io")
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self.assertEqual(SignalSet((self.s1, self.s2)), f.iter_signals())
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def test_self_contained(self):
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f = Fragment()
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f.add_statements(
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self.c1.eq(self.s1),
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self.s1.eq(self.c1)
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)
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f._propagate_ports(ports=(), all_undef_as_ports=True)
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self.assertEqual(f.ports, SignalDict([]))
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def test_infer_input(self):
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f = Fragment()
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f.add_statements(
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self.c1.eq(self.s1)
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)
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f._propagate_ports(ports=(), all_undef_as_ports=True)
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self.assertEqual(f.ports, SignalDict([
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(self.s1, "i")
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]))
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def test_request_output(self):
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f = Fragment()
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f.add_statements(
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self.c1.eq(self.s1)
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)
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f._propagate_ports(ports=(self.c1,), all_undef_as_ports=True)
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self.assertEqual(f.ports, SignalDict([
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(self.s1, "i"),
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(self.c1, "o")
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]))
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def test_input_in_subfragment(self):
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f1 = Fragment()
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f1.add_statements(
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self.c1.eq(self.s1)
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)
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f2 = Fragment()
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f2.add_statements(
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self.s1.eq(0)
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)
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f1.add_subfragment(f2)
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f1._propagate_ports(ports=(), all_undef_as_ports=True)
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self.assertEqual(f1.ports, SignalDict())
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self.assertEqual(f2.ports, SignalDict([
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(self.s1, "o"),
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]))
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def test_input_only_in_subfragment(self):
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f1 = Fragment()
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f2 = Fragment()
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f2.add_statements(
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self.c1.eq(self.s1)
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)
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f1.add_subfragment(f2)
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f1._propagate_ports(ports=(), all_undef_as_ports=True)
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self.assertEqual(f1.ports, SignalDict([
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(self.s1, "i"),
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]))
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self.assertEqual(f2.ports, SignalDict([
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(self.s1, "i"),
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]))
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def test_output_from_subfragment(self):
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f1 = Fragment()
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f1.add_statements(
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self.c1.eq(0)
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)
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f2 = Fragment()
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f2.add_statements(
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self.c2.eq(1)
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)
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f1.add_subfragment(f2)
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f1._propagate_ports(ports=(self.c2,), all_undef_as_ports=True)
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self.assertEqual(f1.ports, SignalDict([
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(self.c2, "o"),
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]))
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self.assertEqual(f2.ports, SignalDict([
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(self.c2, "o"),
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]))
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def test_output_from_subfragment_2(self):
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f1 = Fragment()
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f1.add_statements(
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self.c1.eq(self.s1)
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)
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f2 = Fragment()
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f2.add_statements(
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self.c2.eq(self.s1)
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)
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f1.add_subfragment(f2)
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f3 = Fragment()
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f3.add_statements(
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self.s1.eq(0)
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)
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f2.add_subfragment(f3)
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f1._propagate_ports(ports=(), all_undef_as_ports=True)
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self.assertEqual(f2.ports, SignalDict([
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(self.s1, "o"),
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]))
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def test_input_output_sibling(self):
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f1 = Fragment()
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f2 = Fragment()
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f2.add_statements(
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self.c1.eq(self.c2)
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)
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f1.add_subfragment(f2)
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f3 = Fragment()
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f3.add_statements(
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self.c2.eq(0)
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)
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f3.add_driver(self.c2)
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f1.add_subfragment(f3)
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f1._propagate_ports(ports=(), all_undef_as_ports=True)
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self.assertEqual(f1.ports, SignalDict())
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def test_output_input_sibling(self):
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f1 = Fragment()
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f2 = Fragment()
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f2.add_statements(
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self.c2.eq(0)
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)
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f2.add_driver(self.c2)
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f1.add_subfragment(f2)
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f3 = Fragment()
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f3.add_statements(
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self.c1.eq(self.c2)
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)
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f1.add_subfragment(f3)
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f1._propagate_ports(ports=(), all_undef_as_ports=True)
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self.assertEqual(f1.ports, SignalDict())
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def test_input_cd(self):
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sync = ClockDomain()
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f = Fragment()
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f.add_statements(
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self.c1.eq(self.s1)
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)
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f.add_domains(sync)
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f.add_driver(self.c1, "sync")
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f._propagate_ports(ports=(), all_undef_as_ports=True)
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self.assertEqual(f.ports, SignalDict([
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(self.s1, "i"),
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(sync.clk, "i"),
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(sync.rst, "i"),
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]))
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def test_input_cd_reset_less(self):
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sync = ClockDomain(reset_less=True)
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f = Fragment()
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f.add_statements(
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self.c1.eq(self.s1)
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)
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f.add_domains(sync)
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f.add_driver(self.c1, "sync")
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f._propagate_ports(ports=(), all_undef_as_ports=True)
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self.assertEqual(f.ports, SignalDict([
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(self.s1, "i"),
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(sync.clk, "i"),
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]))
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def test_inout(self):
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s = Signal()
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f1 = Fragment()
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f2 = Instance("foo", io_x=s)
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f1.add_subfragment(f2)
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f1._propagate_ports(ports=(), all_undef_as_ports=True)
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self.assertEqual(f1.ports, SignalDict([
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(s, "io")
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]))
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def test_in_out_same_signal(self):
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s = Signal()
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f1 = Instance("foo", i_x=s, o_y=s)
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f2 = Fragment()
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f2.add_subfragment(f1)
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f2._propagate_ports(ports=(), all_undef_as_ports=True)
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self.assertEqual(f1.ports, SignalDict([
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(s, "o")
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]))
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f3 = Instance("foo", o_y=s, i_x=s)
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f4 = Fragment()
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f4.add_subfragment(f3)
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f4._propagate_ports(ports=(), all_undef_as_ports=True)
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self.assertEqual(f3.ports, SignalDict([
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(s, "o")
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]))
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def test_clk_rst(self):
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sync = ClockDomain()
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f = Fragment()
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f.add_domains(sync)
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f = f.prepare(ports=(ClockSignal("sync"), ResetSignal("sync")))
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self.assertEqual(f.ports, SignalDict([
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(sync.clk, "i"),
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(sync.rst, "i"),
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]))
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def test_port_wrong(self):
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f = Fragment()
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with self.assertRaisesRegex(TypeError,
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r"^Only signals may be added as ports, not \(const 1'd1\)$"):
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f.prepare(ports=(Const(1),))
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def test_port_not_iterable(self):
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f = Fragment()
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with self.assertRaisesRegex(TypeError,
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r"^`ports` must be either a list or a tuple, not 1$"):
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f.prepare(ports=1)
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with self.assertRaisesRegex(TypeError,
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(r"^`ports` must be either a list or a tuple, not \(const 1'd1\)"
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r" \(did you mean `ports=\(<signal>,\)`, rather than `ports=<signal>`\?\)$")):
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f.prepare(ports=Const(1))
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class FragmentDomainsTestCase(FHDLTestCase):
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def test_iter_signals(self):
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cd1 = ClockDomain()
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cd2 = ClockDomain(reset_less=True)
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s1 = Signal()
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s2 = Signal()
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f = Fragment()
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f.add_domains(cd1, cd2)
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f.add_driver(s1, "cd1")
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self.assertEqual(SignalSet((cd1.clk, cd1.rst, s1)), f.iter_signals())
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f.add_driver(s2, "cd2")
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self.assertEqual(SignalSet((cd1.clk, cd1.rst, cd2.clk, s1, s2)), f.iter_signals())
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def test_propagate_up(self):
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cd = ClockDomain()
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f1 = Fragment()
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f2 = Fragment()
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f1.add_subfragment(f2)
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f2.add_domains(cd)
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f1._propagate_domains_up()
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self.assertEqual(f1.domains, {"cd": cd})
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def test_propagate_up_local(self):
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cd = ClockDomain(local=True)
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f1 = Fragment()
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f2 = Fragment()
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f1.add_subfragment(f2)
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f2.add_domains(cd)
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f1._propagate_domains_up()
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self.assertEqual(f1.domains, {})
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def test_domain_conflict(self):
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cda = ClockDomain("sync")
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cdb = ClockDomain("sync")
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fa = Fragment()
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fa.add_domains(cda)
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fb = Fragment()
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fb.add_domains(cdb)
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f = Fragment()
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f.add_subfragment(fa, "a")
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f.add_subfragment(fb, "b")
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f._propagate_domains_up()
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self.assertEqual(f.domains, {"a_sync": cda, "b_sync": cdb})
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(fa, _), (fb, _) = f.subfragments
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self.assertEqual(fa.domains, {"a_sync": cda})
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self.assertEqual(fb.domains, {"b_sync": cdb})
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def test_domain_conflict_anon(self):
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cda = ClockDomain("sync")
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cdb = ClockDomain("sync")
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fa = Fragment()
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fa.add_domains(cda)
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fb = Fragment()
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fb.add_domains(cdb)
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f = Fragment()
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f.add_subfragment(fa, "a")
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f.add_subfragment(fb)
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with self.assertRaisesRegex(DomainError,
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(r"^Domain 'sync' is defined by subfragments 'a', <unnamed #1> of fragment "
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r"'top'; it is necessary to either rename subfragment domains explicitly, "
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r"or give names to subfragments$")):
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f._propagate_domains_up()
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def test_domain_conflict_name(self):
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cda = ClockDomain("sync")
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cdb = ClockDomain("sync")
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fa = Fragment()
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fa.add_domains(cda)
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fb = Fragment()
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fb.add_domains(cdb)
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f = Fragment()
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f.add_subfragment(fa, "x")
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f.add_subfragment(fb, "x")
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with self.assertRaisesRegex(DomainError,
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(r"^Domain 'sync' is defined by subfragments #0, #1 of fragment 'top', some "
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r"of which have identical names; it is necessary to either rename subfragment "
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r"domains explicitly, or give distinct names to subfragments$")):
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f._propagate_domains_up()
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def test_domain_conflict_rename_drivers(self):
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cda = ClockDomain("sync")
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cdb = ClockDomain("sync")
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fa = Fragment()
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fa.add_domains(cda)
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fb = Fragment()
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fb.add_domains(cdb)
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fb.add_driver(ResetSignal("sync"), None)
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f = Fragment()
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f.add_subfragment(fa, "a")
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f.add_subfragment(fb, "b")
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f._propagate_domains_up()
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fb_new, _ = f.subfragments[1]
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self.assertEqual(fb_new.drivers, OrderedDict({
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None: SignalSet((ResetSignal("b_sync"),))
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}))
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def test_domain_conflict_rename_drivers_before_creating_missing(self):
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cda = ClockDomain("sync")
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cdb = ClockDomain("sync")
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s = Signal()
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fa = Fragment()
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fa.add_domains(cda)
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fb = Fragment()
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fb.add_domains(cdb)
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f = Fragment()
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f.add_subfragment(fa, "a")
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f.add_subfragment(fb, "b")
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f.add_driver(s, "b_sync")
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f._propagate_domains(lambda name: ClockDomain(name))
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def test_propagate_down(self):
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cd = ClockDomain()
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f1 = Fragment()
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f2 = Fragment()
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f1.add_domains(cd)
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f1.add_subfragment(f2)
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f1._propagate_domains_down()
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self.assertEqual(f2.domains, {"cd": cd})
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def test_propagate_down_idempotent(self):
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cd = ClockDomain()
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f1 = Fragment()
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f1.add_domains(cd)
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f2 = Fragment()
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f2.add_domains(cd)
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f1.add_subfragment(f2)
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f1._propagate_domains_down()
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self.assertEqual(f1.domains, {"cd": cd})
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self.assertEqual(f2.domains, {"cd": cd})
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def test_propagate(self):
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cd = ClockDomain()
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f1 = Fragment()
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f2 = Fragment()
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f1.add_domains(cd)
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f1.add_subfragment(f2)
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new_domains = f1._propagate_domains(missing_domain=lambda name: None)
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self.assertEqual(f1.domains, {"cd": cd})
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self.assertEqual(f2.domains, {"cd": cd})
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self.assertEqual(new_domains, [])
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def test_propagate_missing(self):
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s1 = Signal()
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f1 = Fragment()
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f1.add_driver(s1, "sync")
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with self.assertRaisesRegex(DomainError,
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r"^Domain 'sync' is used but not defined$"):
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f1._propagate_domains(missing_domain=lambda name: None)
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def test_propagate_create_missing(self):
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s1 = Signal()
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f1 = Fragment()
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f1.add_driver(s1, "sync")
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f2 = Fragment()
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f1.add_subfragment(f2)
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new_domains = f1._propagate_domains(missing_domain=lambda name: ClockDomain(name))
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self.assertEqual(f1.domains.keys(), {"sync"})
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self.assertEqual(f2.domains.keys(), {"sync"})
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self.assertEqual(f1.domains["sync"], f2.domains["sync"])
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self.assertEqual(new_domains, [f1.domains["sync"]])
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def test_propagate_create_missing_fragment(self):
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s1 = Signal()
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f1 = Fragment()
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f1.add_driver(s1, "sync")
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cd = ClockDomain("sync")
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f2 = Fragment()
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|
f2.add_domains(cd)
|
|
|
|
new_domains = f1._propagate_domains(missing_domain=lambda name: f2)
|
|
self.assertEqual(f1.domains.keys(), {"sync"})
|
|
self.assertEqual(f1.domains["sync"], f2.domains["sync"])
|
|
self.assertEqual(new_domains, [])
|
|
self.assertEqual(f1.subfragments, [
|
|
(f2, "cd_sync")
|
|
])
|
|
|
|
def test_propagate_create_missing_fragment_many_domains(self):
|
|
s1 = Signal()
|
|
f1 = Fragment()
|
|
f1.add_driver(s1, "sync")
|
|
|
|
cd_por = ClockDomain("por")
|
|
cd_sync = ClockDomain("sync")
|
|
f2 = Fragment()
|
|
f2.add_domains(cd_por, cd_sync)
|
|
|
|
new_domains = f1._propagate_domains(missing_domain=lambda name: f2)
|
|
self.assertEqual(f1.domains.keys(), {"sync", "por"})
|
|
self.assertEqual(f2.domains.keys(), {"sync", "por"})
|
|
self.assertEqual(f1.domains["sync"], f2.domains["sync"])
|
|
self.assertEqual(new_domains, [])
|
|
self.assertEqual(f1.subfragments, [
|
|
(f2, "cd_sync")
|
|
])
|
|
|
|
def test_propagate_create_missing_fragment_wrong(self):
|
|
s1 = Signal()
|
|
f1 = Fragment()
|
|
f1.add_driver(s1, "sync")
|
|
|
|
f2 = Fragment()
|
|
f2.add_domains(ClockDomain("foo"))
|
|
|
|
with self.assertRaisesRegex(DomainError,
|
|
(r"^Fragment returned by missing domain callback does not define requested "
|
|
r"domain 'sync' \(defines 'foo'\)\.$")):
|
|
f1._propagate_domains(missing_domain=lambda name: f2)
|
|
|
|
|
|
class FragmentHierarchyConflictTestCase(FHDLTestCase):
|
|
def setUp_self_sub(self):
|
|
self.s1 = Signal()
|
|
self.c1 = Signal()
|
|
self.c2 = Signal()
|
|
|
|
self.f1 = Fragment()
|
|
self.f1.add_statements(self.c1.eq(0))
|
|
self.f1.add_driver(self.s1)
|
|
self.f1.add_driver(self.c1, "sync")
|
|
|
|
self.f1a = Fragment()
|
|
self.f1.add_subfragment(self.f1a, "f1a")
|
|
|
|
self.f2 = Fragment()
|
|
self.f2.add_statements(self.c2.eq(1))
|
|
self.f2.add_driver(self.s1)
|
|
self.f2.add_driver(self.c2, "sync")
|
|
self.f1.add_subfragment(self.f2)
|
|
|
|
self.f1b = Fragment()
|
|
self.f1.add_subfragment(self.f1b, "f1b")
|
|
|
|
self.f2a = Fragment()
|
|
self.f2.add_subfragment(self.f2a, "f2a")
|
|
|
|
def test_conflict_self_sub(self):
|
|
self.setUp_self_sub()
|
|
|
|
self.f1._resolve_hierarchy_conflicts(mode="silent")
|
|
self.assertEqual(self.f1.subfragments, [
|
|
(self.f1a, "f1a"),
|
|
(self.f1b, "f1b"),
|
|
(self.f2a, "f2a"),
|
|
])
|
|
self.assertRepr(self.f1.statements, """
|
|
(
|
|
(eq (sig c1) (const 1'd0))
|
|
(eq (sig c2) (const 1'd1))
|
|
)
|
|
""")
|
|
self.assertEqual(self.f1.drivers, {
|
|
None: SignalSet((self.s1,)),
|
|
"sync": SignalSet((self.c1, self.c2)),
|
|
})
|
|
|
|
def test_conflict_self_sub_error(self):
|
|
self.setUp_self_sub()
|
|
|
|
with self.assertRaisesRegex(DriverConflict,
|
|
r"^Signal '\(sig s1\)' is driven from multiple fragments: top, top.<unnamed #1>$"):
|
|
self.f1._resolve_hierarchy_conflicts(mode="error")
|
|
|
|
def test_conflict_self_sub_warning(self):
|
|
self.setUp_self_sub()
|
|
|
|
with self.assertWarnsRegex(DriverConflict,
|
|
(r"^Signal '\(sig s1\)' is driven from multiple fragments: top, top.<unnamed #1>; "
|
|
r"hierarchy will be flattened$")):
|
|
self.f1._resolve_hierarchy_conflicts(mode="warn")
|
|
|
|
def setUp_sub_sub(self):
|
|
self.s1 = Signal()
|
|
self.c1 = Signal()
|
|
self.c2 = Signal()
|
|
|
|
self.f1 = Fragment()
|
|
|
|
self.f2 = Fragment()
|
|
self.f2.add_driver(self.s1)
|
|
self.f2.add_statements(self.c1.eq(0))
|
|
self.f1.add_subfragment(self.f2)
|
|
|
|
self.f3 = Fragment()
|
|
self.f3.add_driver(self.s1)
|
|
self.f3.add_statements(self.c2.eq(1))
|
|
self.f1.add_subfragment(self.f3)
|
|
|
|
def test_conflict_sub_sub(self):
|
|
self.setUp_sub_sub()
|
|
|
|
self.f1._resolve_hierarchy_conflicts(mode="silent")
|
|
self.assertEqual(self.f1.subfragments, [])
|
|
self.assertRepr(self.f1.statements, """
|
|
(
|
|
(eq (sig c1) (const 1'd0))
|
|
(eq (sig c2) (const 1'd1))
|
|
)
|
|
""")
|
|
|
|
def setUp_self_subsub(self):
|
|
self.s1 = Signal()
|
|
self.c1 = Signal()
|
|
self.c2 = Signal()
|
|
|
|
self.f1 = Fragment()
|
|
self.f1.add_driver(self.s1)
|
|
|
|
self.f2 = Fragment()
|
|
self.f2.add_statements(self.c1.eq(0))
|
|
self.f1.add_subfragment(self.f2)
|
|
|
|
self.f3 = Fragment()
|
|
self.f3.add_driver(self.s1)
|
|
self.f3.add_statements(self.c2.eq(1))
|
|
self.f2.add_subfragment(self.f3)
|
|
|
|
def test_conflict_self_subsub(self):
|
|
self.setUp_self_subsub()
|
|
|
|
self.f1._resolve_hierarchy_conflicts(mode="silent")
|
|
self.assertEqual(self.f1.subfragments, [])
|
|
self.assertRepr(self.f1.statements, """
|
|
(
|
|
(eq (sig c1) (const 1'd0))
|
|
(eq (sig c2) (const 1'd1))
|
|
)
|
|
""")
|
|
|
|
def test_explicit_flatten(self):
|
|
self.f1 = Fragment()
|
|
self.f2 = Fragment()
|
|
self.f2.flatten = True
|
|
self.f1.add_subfragment(self.f2)
|
|
|
|
self.f1._resolve_hierarchy_conflicts(mode="silent")
|
|
self.assertEqual(self.f1.subfragments, [])
|
|
|
|
def test_no_conflict_local_domains(self):
|
|
f1 = Fragment()
|
|
cd1 = ClockDomain("d", local=True)
|
|
f1.add_domains(cd1)
|
|
f1.add_driver(ClockSignal("d"))
|
|
f2 = Fragment()
|
|
cd2 = ClockDomain("d", local=True)
|
|
f2.add_domains(cd2)
|
|
f2.add_driver(ClockSignal("d"))
|
|
f3 = Fragment()
|
|
f3.add_subfragment(f1)
|
|
f3.add_subfragment(f2)
|
|
f3.prepare()
|
|
|
|
|
|
class InstanceTestCase(FHDLTestCase):
|
|
def test_construct(self):
|
|
s1 = Signal()
|
|
s2 = Signal()
|
|
s3 = Signal()
|
|
s4 = Signal()
|
|
s5 = Signal()
|
|
s6 = Signal()
|
|
inst = Instance("foo",
|
|
("a", "ATTR1", 1),
|
|
("p", "PARAM1", 0x1234),
|
|
("i", "s1", s1),
|
|
("o", "s2", s2),
|
|
("io", "s3", s3),
|
|
a_ATTR2=2,
|
|
p_PARAM2=0x5678,
|
|
i_s4=s4,
|
|
o_s5=s5,
|
|
io_s6=s6,
|
|
)
|
|
self.assertEqual(inst.attrs, OrderedDict([
|
|
("ATTR1", 1),
|
|
("ATTR2", 2),
|
|
]))
|
|
self.assertEqual(inst.parameters, OrderedDict([
|
|
("PARAM1", 0x1234),
|
|
("PARAM2", 0x5678),
|
|
]))
|
|
self.assertEqual(inst.named_ports, OrderedDict([
|
|
("s1", (s1, "i")),
|
|
("s2", (s2, "o")),
|
|
("s3", (s3, "io")),
|
|
("s4", (s4, "i")),
|
|
("s5", (s5, "o")),
|
|
("s6", (s6, "io")),
|
|
]))
|
|
|
|
def test_cast_ports(self):
|
|
inst = Instance("foo",
|
|
("i", "s1", 1),
|
|
("o", "s2", 2),
|
|
("io", "s3", 3),
|
|
i_s4=4,
|
|
o_s5=5,
|
|
io_s6=6,
|
|
)
|
|
self.assertRepr(inst.named_ports["s1"][0], "(const 1'd1)")
|
|
self.assertRepr(inst.named_ports["s2"][0], "(const 2'd2)")
|
|
self.assertRepr(inst.named_ports["s3"][0], "(const 2'd3)")
|
|
self.assertRepr(inst.named_ports["s4"][0], "(const 3'd4)")
|
|
self.assertRepr(inst.named_ports["s5"][0], "(const 3'd5)")
|
|
self.assertRepr(inst.named_ports["s6"][0], "(const 3'd6)")
|
|
|
|
def test_wrong_construct_arg(self):
|
|
s = Signal()
|
|
with self.assertRaisesRegex(NameError,
|
|
(r"^Instance argument \('', 's1', \(sig s\)\) should be a tuple "
|
|
r"\(kind, name, value\) where kind is one of \"a\", \"p\", \"i\", \"o\", or \"io\"$")):
|
|
Instance("foo", ("", "s1", s))
|
|
|
|
def test_wrong_construct_kwarg(self):
|
|
s = Signal()
|
|
with self.assertRaisesRegex(NameError,
|
|
(r"^Instance keyword argument x_s1=\(sig s\) does not start with one of "
|
|
r"\"a_\", \"p_\", \"i_\", \"o_\", or \"io_\"$")):
|
|
Instance("foo", x_s1=s)
|
|
|
|
def setUp_cpu(self):
|
|
self.rst = Signal()
|
|
self.stb = Signal()
|
|
self.pins = Signal(8)
|
|
self.datal = Signal(4)
|
|
self.datah = Signal(4)
|
|
self.inst = Instance("cpu",
|
|
p_RESET=0x1234,
|
|
i_clk=ClockSignal(),
|
|
i_rst=self.rst,
|
|
o_stb=self.stb,
|
|
o_data=Cat(self.datal, self.datah),
|
|
io_pins=self.pins[:]
|
|
)
|
|
self.wrap = Fragment()
|
|
self.wrap.add_subfragment(self.inst)
|
|
|
|
def test_init(self):
|
|
self.setUp_cpu()
|
|
f = self.inst
|
|
self.assertEqual(f.type, "cpu")
|
|
self.assertEqual(f.parameters, OrderedDict([("RESET", 0x1234)]))
|
|
self.assertEqual(list(f.named_ports.keys()), ["clk", "rst", "stb", "data", "pins"])
|
|
self.assertEqual(f.ports, SignalDict([]))
|
|
|
|
def test_prepare(self):
|
|
self.setUp_cpu()
|
|
f = self.wrap.prepare()
|
|
sync_clk = f.domains["sync"].clk
|
|
self.assertEqual(f.ports, SignalDict([
|
|
(sync_clk, "i"),
|
|
(self.rst, "i"),
|
|
(self.pins, "io"),
|
|
]))
|
|
|
|
def test_prepare_explicit_ports(self):
|
|
self.setUp_cpu()
|
|
f = self.wrap.prepare(ports=[self.rst, self.stb])
|
|
sync_clk = f.domains["sync"].clk
|
|
sync_rst = f.domains["sync"].rst
|
|
self.assertEqual(f.ports, SignalDict([
|
|
(sync_clk, "i"),
|
|
(sync_rst, "i"),
|
|
(self.rst, "i"),
|
|
(self.stb, "o"),
|
|
(self.pins, "io"),
|
|
]))
|
|
|
|
def test_prepare_slice_in_port(self):
|
|
s = Signal(2)
|
|
f = Fragment()
|
|
f.add_subfragment(Instance("foo", o_O=s[0]))
|
|
f.add_subfragment(Instance("foo", o_O=s[1]))
|
|
fp = f.prepare(ports=[s], missing_domain=lambda name: None)
|
|
self.assertEqual(fp.ports, SignalDict([
|
|
(s, "o"),
|
|
]))
|
|
|
|
def test_prepare_attrs(self):
|
|
self.setUp_cpu()
|
|
self.inst.attrs["ATTR"] = 1
|
|
f = self.inst.prepare()
|
|
self.assertEqual(f.attrs, OrderedDict([
|
|
("ATTR", 1),
|
|
]))
|
|
|
|
def test_assign_names_to_signals(self):
|
|
i = Signal()
|
|
rst = Signal()
|
|
o1 = Signal()
|
|
o2 = Signal()
|
|
o3 = Signal()
|
|
i1 = Signal(name="i")
|
|
|
|
f = Fragment()
|
|
f.add_domains(cd_sync := ClockDomain())
|
|
f.add_domains(cd_sync_norst := ClockDomain(reset_less=True))
|
|
f.add_ports((i, rst), dir="i")
|
|
f.add_ports((o1, o2, o3), dir="o")
|
|
f.add_statements([o1.eq(0)])
|
|
f.add_driver(o1, domain=None)
|
|
f.add_statements([o2.eq(i1)])
|
|
f.add_driver(o2, domain="sync")
|
|
f.add_statements([o3.eq(i1)])
|
|
f.add_driver(o3, domain="sync_norst")
|
|
|
|
names = f._assign_names_to_signals()
|
|
self.assertEqual(names, SignalDict([
|
|
(i, "i"),
|
|
(rst, "rst"),
|
|
(o1, "o1"),
|
|
(o2, "o2"),
|
|
(o3, "o3"),
|
|
(cd_sync.clk, "clk"),
|
|
(cd_sync.rst, "rst$6"),
|
|
(cd_sync_norst.clk, "sync_norst_clk"),
|
|
(i1, "i$8"),
|
|
]))
|
|
|
|
def test_assign_names_to_fragments(self):
|
|
f = Fragment()
|
|
f.add_subfragment(a := Fragment())
|
|
f.add_subfragment(b := Fragment(), name="b")
|
|
|
|
names = f._assign_names_to_fragments()
|
|
self.assertEqual(names, {
|
|
f: ("top",),
|
|
a: ("top", "U$0"),
|
|
b: ("top", "b")
|
|
})
|
|
|
|
def test_assign_names_to_fragments_rename_top(self):
|
|
f = Fragment()
|
|
f.add_subfragment(a := Fragment())
|
|
f.add_subfragment(b := Fragment(), name="b")
|
|
|
|
names = f._assign_names_to_fragments(hierarchy=("bench", "cpu"))
|
|
self.assertEqual(names, {
|
|
f: ("bench", "cpu",),
|
|
a: ("bench", "cpu", "U$0"),
|
|
b: ("bench", "cpu", "b")
|
|
})
|
|
|
|
def test_assign_names_to_fragments_collide_with_signal(self):
|
|
f = Fragment()
|
|
f.add_subfragment(a_f := Fragment(), name="a")
|
|
f.add_ports((a_s := Signal(name="a"),), dir="o")
|
|
|
|
names = f._assign_names_to_fragments()
|
|
self.assertEqual(names, {
|
|
f: ("top",),
|
|
a_f: ("top", "a$U$0")
|
|
})
|