whitequark 97af266645 back.verilog: allow stripping the src attribute, for cleaner output.		2019-04-22 14:59:53 +00:00
..
__init__.py	Initial commit.	2018-12-12 03:18:44 +00:00
pysim.py	back.pysim: support async reset.	2019-01-26 18:07:43 +00:00
rtlil.py	hdl.ir: rework named port handling for Instances.	2019-04-22 07:46:47 +00:00
verilog.py	back.verilog: allow stripping the src attribute, for cleaner output.	2019-04-22 14:59:53 +00:00