whitequark 3ac13eb8f9 back.rtlil: don't emit wires for empty signals. ... Fixes #312.		2020-01-31 03:38:58 +00:00
..
__init__.py	Initial commit.	2018-12-12 03:18:44 +00:00
pysim.py	back.pysim: fix miscompilation of Signal(unsigned) - Signal(signed).	2019-12-02 18:52:55 +00:00
rtlil.py	back.rtlil: don't emit wires for empty signals.	2020-01-31 03:38:58 +00:00
verilog.py	back.verilog: remove $verilog_initial_trigger after proc_prune.	2019-10-28 10:11:41 +00:00