whitequark a2241fcfdb back.{rtlil,verilog}: split convert_fragment() off convert(). ... Because Fragment.prepare is not (currently) idempotent, it is useful to be able to avoid calling it when converting. Even if it is made idempotent, it can be slow on large designs, so it is advantageous regardless of that.		2019-08-19 19:49:51 +00:00
..
fhdl	back.{rtlil,verilog}: split convert_fragment() off convert().	2019-08-19 19:49:51 +00:00
genlib	compat.genlib.fsm: fix after commit dac62754.	2019-07-08 10:12:26 +00:00
sim	hdl.ir: call back from Fragment.prepare if a clock domain is missing.	2019-08-03 14:54:20 +00:00
__init__.py	compat.fhdl.decorators: port from oMigen.	2019-08-08 08:09:28 +00:00