whitequark 07a3685da8 back.rtlil: do not squash empty modules. ... In commit 9faa1d37, the RTLIL backend was changed to ignore modules without ports completely, since Yosys would recognize empty modules as black boxes without explicit `write_verilog -noblackbox` and break the design. That change had many flaws: * It removed instances without ports, which are used in e.g. SoC FPGAs to instantiate a dummy CPU. * It removed fragments without ports, which can appear in e.g. SoC FPGAs in case the fabric is not connected to any I/O ports. * Finally, it was just conceptually unjustified. This commit changes the logic to actually check for empty fragments, and instead of removing them, it adds a dummy wire inside. It would be possible to use the Yosys-specific (*noblackbox*) attribute. However, it would be necessary to strip it for most targets right away, and also the wire doubles as documentation. Fixes #441.		2020-08-26 22:45:19 +00:00
..
__init__.py	Initial commit.	2018-12-12 03:18:44 +00:00
cxxrtl.py	back.cxxrtl: actualize Yosys version requirement.	2020-08-26 09:16:46 +00:00
pysim.py	back.pysim→sim.pysim; split into more manageable parts.	2020-07-08 12:49:38 +00:00
rtlil.py	back.rtlil: do not squash empty modules.	2020-08-26 22:45:19 +00:00
verilog.py	back.verilog: omit Verilog initial trigger only if Yosys adds it.	2020-08-26 16:51:12 +00:00