9f643ce005
This commit:
* moves lists of universally useful imports from `nmigen` to
`nmigen.hdl` and `nmigen.lib`, reimporting them in `nmigen`;
* replaces lots of imports from individual parts of `nmigen.hdl`
with a star import from `nmigen.hdl`;
* replaces imports in tests with what we expect downstream code
to use;
* adds some missing imports in `nmigen.formal`.
82 lines
2.6 KiB
Python
82 lines
2.6 KiB
Python
from .tools import *
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from ..hdl import *
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from ..back.pysim import *
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from ..lib.cdc import *
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class MultiRegTestCase(FHDLTestCase):
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def test_basic(self):
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i = Signal()
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o = Signal()
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frag = MultiReg(i, o)
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with Simulator(frag) as sim:
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sim.add_clock(1e-6)
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def process():
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self.assertEqual((yield o), 0)
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yield i.eq(1)
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yield Tick()
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self.assertEqual((yield o), 0)
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yield Tick()
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self.assertEqual((yield o), 0)
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yield Tick()
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self.assertEqual((yield o), 1)
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sim.add_process(process)
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sim.run()
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def test_reset_value(self):
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i = Signal(reset=1)
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o = Signal()
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frag = MultiReg(i, o, reset=1)
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with Simulator(frag) as sim:
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sim.add_clock(1e-6)
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def process():
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self.assertEqual((yield o), 1)
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yield i.eq(0)
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yield Tick()
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self.assertEqual((yield o), 1)
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yield Tick()
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self.assertEqual((yield o), 1)
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yield Tick()
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self.assertEqual((yield o), 0)
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sim.add_process(process)
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sim.run()
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class ResetSynchronizerTestCase(FHDLTestCase):
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def test_basic(self):
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arst = Signal()
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m = Module()
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m.domains += ClockDomain("sync")
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m.submodules += ResetSynchronizer(arst)
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s = Signal(reset=1)
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m.d.sync += s.eq(0)
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with Simulator(m, vcd_file=open("test.vcd", "w")) as sim:
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sim.add_clock(1e-6)
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def process():
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# initial reset
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self.assertEqual((yield s), 1)
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yield Tick(); yield Delay(1e-8)
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self.assertEqual((yield s), 1)
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yield Tick(); yield Delay(1e-8)
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self.assertEqual((yield s), 1)
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yield Tick(); yield Delay(1e-8)
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self.assertEqual((yield s), 0)
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yield Tick(); yield Delay(1e-8)
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yield arst.eq(1)
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yield Delay(1e-8)
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self.assertEqual((yield s), 1)
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yield Tick(); yield Delay(1e-8)
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self.assertEqual((yield s), 1)
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yield arst.eq(0)
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yield Tick(); yield Delay(1e-8)
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self.assertEqual((yield s), 1)
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yield Tick(); yield Delay(1e-8)
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self.assertEqual((yield s), 1)
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yield Tick(); yield Delay(1e-8)
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self.assertEqual((yield s), 0)
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yield Tick(); yield Delay(1e-8)
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sim.add_process(process)
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sim.run()
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