22 lines
565 B
Python
22 lines
565 B
Python
from nmigen import *
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from nmigen.back import rtlil, verilog
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class ClockDivisor:
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def __init__(self, factor):
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self.v = Signal(factor)
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self.o = Signal()
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def get_fragment(self, platform):
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m = Module()
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m.d.sync += self.v.eq(self.v + 1)
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m.d.comb += self.o.eq(self.v[-1])
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return m.lower(platform)
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ctr = ClockDivisor(factor=16)
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frag = ctr.get_fragment(platform=None)
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frag.add_domains(ClockDomain("sync", async_reset=True))
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# print(rtlil.convert(frag, ports=[ctr.o]))
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print(verilog.convert(frag, ports=[ctr.o]))
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