77dab7884c
This renames the `FrozenMemory` exception to `AlreadyElaborated` and reuses it for modules. Fixes #1350.
454 lines
21 KiB
Python
454 lines
21 KiB
Python
# amaranth: UnusedElaboratable=no
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from amaranth.hdl import *
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from amaranth.hdl._mem import MemoryInstance
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from amaranth.lib import memory, data
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from amaranth.lib.wiring import In, Out, SignatureMembers
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from .utils import *
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class MyStruct(data.Struct):
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a: unsigned(3)
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b: signed(2)
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class WritePortTestCase(FHDLTestCase):
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def test_signature(self):
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sig = memory.WritePort.Signature(addr_width=2, shape=signed(4))
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self.assertEqual(sig.addr_width, 2)
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self.assertEqual(sig.shape, signed(4))
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self.assertEqual(sig.granularity, None)
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self.assertEqual(sig.members, SignatureMembers({
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"addr": In(2),
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"data": In(signed(4)),
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"en": In(1),
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}))
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sig = memory.WritePort.Signature(addr_width=2, shape=8, granularity=2)
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self.assertEqual(sig.addr_width, 2)
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self.assertEqual(sig.shape, 8)
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self.assertEqual(sig.members, SignatureMembers({
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"addr": In(2),
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"data": In(8),
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"en": In(4),
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}))
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sig = memory.WritePort.Signature(addr_width=2, shape=data.ArrayLayout(9, 8), granularity=2)
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self.assertEqual(sig.addr_width, 2)
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self.assertEqual(sig.shape, data.ArrayLayout(9, 8))
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self.assertEqual(sig.members, SignatureMembers({
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"addr": In(2),
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"data": In(data.ArrayLayout(9, 8)),
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"en": In(4),
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}))
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sig = memory.WritePort.Signature(addr_width=2, shape=0, granularity=0)
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self.assertEqual(sig.addr_width, 2)
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self.assertEqual(sig.shape, 0)
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self.assertEqual(sig.members, SignatureMembers({
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"addr": In(2),
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"data": In(0),
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"en": In(0),
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}))
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sig = memory.WritePort.Signature(addr_width=2, shape=data.ArrayLayout(9, 0), granularity=0)
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self.assertEqual(sig.addr_width, 2)
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self.assertEqual(sig.shape, data.ArrayLayout(9, 0))
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self.assertEqual(sig.members, SignatureMembers({
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"addr": In(2),
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"data": In(data.ArrayLayout(9, 0)),
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"en": In(0),
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}))
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def test_signature_wrong(self):
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with self.assertRaisesRegex(TypeError,
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r"^Address width must be a non-negative integer, not -2$"):
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memory.WritePort.Signature(addr_width=-2, shape=8)
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with self.assertRaisesRegex(TypeError,
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r"^Granularity must be a non-negative integer or None, not -2$"):
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memory.WritePort.Signature(addr_width=4, shape=8, granularity=-2)
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with self.assertRaisesRegex(ValueError,
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r"^Granularity cannot be specified for a memory with a signed shape$"):
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memory.WritePort.Signature(addr_width=2, shape=signed(8), granularity=2)
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with self.assertRaisesRegex(TypeError,
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r"^Granularity can only be specified for memories whose shape is unsigned or "
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r"data.ArrayLayout$"):
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memory.WritePort.Signature(addr_width=2, shape=MyStruct, granularity=2)
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with self.assertRaisesRegex(ValueError,
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r"^Granularity must be positive$"):
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memory.WritePort.Signature(addr_width=2, shape=8, granularity=0)
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with self.assertRaisesRegex(ValueError,
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r"^Granularity must be positive$"):
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memory.WritePort.Signature(addr_width=2, shape=data.ArrayLayout(8, 8), granularity=0)
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with self.assertRaisesRegex(ValueError,
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r"^Granularity must evenly divide data width$"):
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memory.WritePort.Signature(addr_width=2, shape=8, granularity=3)
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with self.assertRaisesRegex(ValueError,
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r"^Granularity must evenly divide data array length$"):
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memory.WritePort.Signature(addr_width=2, shape=data.ArrayLayout(8, 8), granularity=3)
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def test_signature_eq(self):
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sig = memory.WritePort.Signature(addr_width=2, shape=8)
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self.assertEqual(sig, memory.WritePort.Signature(addr_width=2, shape=8))
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self.assertNotEqual(sig, memory.WritePort.Signature(addr_width=2, shape=7))
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self.assertNotEqual(sig, memory.WritePort.Signature(addr_width=1, shape=8))
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self.assertNotEqual(sig, memory.WritePort.Signature(addr_width=2, shape=8, granularity=8))
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sig = memory.WritePort.Signature(addr_width=2, shape=8, granularity=4)
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self.assertEqual(sig, memory.WritePort.Signature(addr_width=2, shape=8, granularity=4))
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self.assertNotEqual(sig, memory.WritePort.Signature(addr_width=2, shape=8, granularity=8))
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def test_constructor(self):
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signature = memory.WritePort.Signature(shape=MyStruct, addr_width=4)
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port = memory.WritePort(signature, memory=None, domain="sync")
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self.assertEqual(port.signature, signature)
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self.assertIsNone(port.memory)
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self.assertEqual(port.domain, "sync")
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self.assertIsInstance(port.addr, Signal)
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self.assertEqual(port.addr.shape(), unsigned(4))
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self.assertIsInstance(port.data, data.View)
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self.assertEqual(port.data.shape(), MyStruct)
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self.assertIsInstance(port.en, Signal)
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self.assertEqual(port.en.shape(), unsigned(1))
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signature = memory.WritePort.Signature(shape=8, addr_width=4, granularity=2)
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port = memory.WritePort(signature, memory=None, domain="sync")
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self.assertEqual(port.signature, signature)
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self.assertIsNone(port.memory)
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self.assertEqual(port.domain, "sync")
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self.assertIsInstance(port.addr, Signal)
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self.assertEqual(port.addr.shape(), unsigned(4))
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self.assertIsInstance(port.data, Signal)
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self.assertEqual(port.data.shape(), unsigned(8))
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self.assertIsInstance(port.en, Signal)
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self.assertEqual(port.en.shape(), unsigned(4))
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m = memory.Memory(depth=16, shape=8, init=[])
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port = memory.WritePort(signature, memory=m, domain="sync")
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self.assertIs(port.memory, m)
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self.assertEqual(m.write_ports, (port,))
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signature = memory.WritePort.Signature(shape=MyStruct, addr_width=4)
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port = signature.create()
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self.assertEqual(port.signature, signature)
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self.assertIsNone(port.memory)
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self.assertEqual(port.domain, "sync")
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self.assertRepr(port.addr, "(sig port__addr)")
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port = signature.create(path=("abc",))
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self.assertRepr(port.addr, "(sig abc__addr)")
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def test_constructor_wrong(self):
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signature = memory.ReadPort.Signature(shape=8, addr_width=4)
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with self.assertRaisesRegex(TypeError,
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r"^Expected signature to be WritePort.Signature, not ReadPort.Signature\(.*\)$"):
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memory.WritePort(signature, memory=None, domain="sync")
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signature = memory.WritePort.Signature(shape=8, addr_width=4, granularity=2)
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with self.assertRaisesRegex(TypeError,
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r"^Domain must be a string, not None$"):
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memory.WritePort(signature, memory=None, domain=None)
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with self.assertRaisesRegex(TypeError,
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r"^Expected memory to be Memory or None, not 'a'$"):
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memory.WritePort(signature, memory="a", domain="sync")
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with self.assertRaisesRegex(ValueError,
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r"^Write ports cannot be asynchronous$"):
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memory.WritePort(signature, memory=None, domain="comb")
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signature = memory.WritePort.Signature(shape=8, addr_width=4)
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m = memory.Memory(depth=8, shape=8, init=[])
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with self.assertRaisesRegex(ValueError,
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r"^Memory address width 3 doesn't match port address width 4$"):
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memory.WritePort(signature, memory=m, domain="sync")
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m = memory.Memory(depth=16, shape=signed(8), init=[])
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with self.assertRaisesRegex(ValueError,
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r"^Memory shape signed\(8\) doesn't match port shape 8$"):
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memory.WritePort(signature, memory=m, domain="sync")
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class ReadPortTestCase(FHDLTestCase):
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def test_signature(self):
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sig = memory.ReadPort.Signature(addr_width=2, shape=signed(4))
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self.assertEqual(sig.addr_width, 2)
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self.assertEqual(sig.shape, signed(4))
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self.assertEqual(sig.members, SignatureMembers({
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"addr": In(2),
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"data": Out(signed(4)),
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"en": In(1, init=1),
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}))
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sig = memory.ReadPort.Signature(addr_width=2, shape=8)
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self.assertEqual(sig.addr_width, 2)
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self.assertEqual(sig.shape, 8)
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self.assertEqual(sig.members, SignatureMembers({
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"addr": In(2),
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"data": Out(8),
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"en": In(1, init=1),
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}))
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sig = memory.ReadPort.Signature(addr_width=2, shape=MyStruct)
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self.assertEqual(sig.addr_width, 2)
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self.assertEqual(sig.shape, MyStruct)
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self.assertEqual(sig.members, SignatureMembers({
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"addr": In(2),
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"data": Out(MyStruct),
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"en": In(1, init=1),
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}))
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def test_signature_wrong(self):
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with self.assertRaisesRegex(TypeError,
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"^Address width must be a non-negative integer, not -2$"):
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memory.ReadPort.Signature(addr_width=-2, shape=8)
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def test_signature_eq(self):
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sig = memory.ReadPort.Signature(addr_width=2, shape=8)
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self.assertEqual(sig, memory.ReadPort.Signature(addr_width=2, shape=8))
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self.assertNotEqual(sig, memory.ReadPort.Signature(addr_width=2, shape=7))
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self.assertNotEqual(sig, memory.ReadPort.Signature(addr_width=1, shape=8))
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self.assertNotEqual(sig, memory.WritePort.Signature(addr_width=2, shape=8))
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def test_constructor(self):
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signature = memory.ReadPort.Signature(shape=MyStruct, addr_width=4)
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port = memory.ReadPort(signature, memory=None, domain="sync")
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self.assertEqual(port.signature, signature)
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self.assertIsNone(port.memory)
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self.assertEqual(port.domain, "sync")
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self.assertIsInstance(port.addr, Signal)
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self.assertEqual(port.addr.shape(), unsigned(4))
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self.assertIsInstance(port.data, data.View)
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self.assertEqual(port.data.shape(), MyStruct)
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self.assertIsInstance(port.en, Signal)
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self.assertEqual(port.en.shape(), unsigned(1))
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self.assertEqual(port.transparent_for, ())
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signature = memory.ReadPort.Signature(shape=8, addr_width=4)
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port = memory.ReadPort(signature, memory=None, domain="comb")
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self.assertEqual(port.signature, signature)
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self.assertIsNone(port.memory)
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self.assertEqual(port.domain, "comb")
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self.assertIsInstance(port.addr, Signal)
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self.assertEqual(port.addr.shape(), unsigned(4))
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self.assertIsInstance(port.data, Signal)
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self.assertEqual(port.data.shape(), unsigned(8))
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self.assertIsInstance(port.en, Const)
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self.assertEqual(port.en.shape(), unsigned(1))
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self.assertEqual(port.en.value, 1)
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self.assertEqual(port.transparent_for, ())
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m = memory.Memory(depth=16, shape=8, init=[])
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port = memory.ReadPort(signature, memory=m, domain="sync")
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self.assertIs(port.memory, m)
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self.assertEqual(m.read_ports, (port,))
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write_port = m.write_port()
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port = memory.ReadPort(signature, memory=m, domain="sync", transparent_for=[write_port])
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self.assertIs(port.memory, m)
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self.assertEqual(port.transparent_for, (write_port,))
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signature = memory.ReadPort.Signature(shape=MyStruct, addr_width=4)
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port = signature.create()
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self.assertEqual(port.signature, signature)
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self.assertIsNone(port.memory)
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self.assertEqual(port.domain, "sync")
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self.assertRepr(port.addr, "(sig port__addr)")
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port = signature.create(path=("abc",))
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self.assertRepr(port.addr, "(sig abc__addr)")
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def test_constructor_wrong(self):
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signature = memory.WritePort.Signature(shape=8, addr_width=4)
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with self.assertRaisesRegex(TypeError,
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r"^Expected signature to be ReadPort.Signature, not WritePort.Signature\(.*\)$"):
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memory.ReadPort(signature, memory=None, domain="sync")
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signature = memory.ReadPort.Signature(shape=8, addr_width=4)
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with self.assertRaisesRegex(TypeError,
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r"^Domain must be a string, not None$"):
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memory.ReadPort(signature, memory=None, domain=None)
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with self.assertRaisesRegex(TypeError,
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r"^Expected memory to be Memory or None, not 'a'$"):
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memory.ReadPort(signature, memory="a", domain="sync")
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signature = memory.ReadPort.Signature(shape=8, addr_width=4)
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m = memory.Memory(depth=8, shape=8, init=[])
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with self.assertRaisesRegex(ValueError,
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r"^Memory address width 3 doesn't match port address width 4$"):
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memory.ReadPort(signature, memory=m, domain="sync")
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m = memory.Memory(depth=16, shape=signed(8), init=[])
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with self.assertRaisesRegex(ValueError,
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r"^Memory shape signed\(8\) doesn't match port shape 8$"):
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memory.ReadPort(signature, memory=m, domain="sync")
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m = memory.Memory(depth=16, shape=8, init=[])
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port = m.read_port()
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with self.assertRaisesRegex(TypeError,
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r"^Transparency set must contain only WritePort instances$"):
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memory.ReadPort(signature, memory=m, domain="sync", transparent_for=[port])
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write_port = m.write_port()
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m2 = memory.Memory(depth=16, shape=8, init=[])
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with self.assertRaisesRegex(ValueError,
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r"^Ports in transparency set must belong to the same memory$"):
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memory.ReadPort(signature, memory=m2, domain="sync", transparent_for=[write_port])
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with self.assertRaisesRegex(ValueError,
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r"^Ports in transparency set must belong to the same domain$"):
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memory.ReadPort(signature, memory=m, domain="other", transparent_for=[write_port])
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class MemoryTestCase(FHDLTestCase):
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def test_constructor(self):
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m = memory.Memory(shape=8, depth=4, init=[1, 2, 3])
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self.assertEqual(m.shape, 8)
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self.assertEqual(m.depth, 4)
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self.assertEqual(m.init.shape, 8)
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self.assertEqual(len(m.init), 4)
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self.assertEqual(m.attrs, {})
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self.assertIsInstance(m.init, MemoryData.Init)
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self.assertEqual(list(m.init), [1, 2, 3, 0])
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self.assertEqual(m.init._raw, [1, 2, 3, 0])
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self.assertRepr(m.init, "MemoryData.Init([1, 2, 3, 0], shape=8, depth=4)")
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self.assertEqual(m.read_ports, ())
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self.assertEqual(m.write_ports, ())
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data = MemoryData(shape=8, depth=4, init=[1, 2, 3])
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m = memory.Memory(data)
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self.assertIs(m.data, data)
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self.assertEqual(m.shape, 8)
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self.assertEqual(m.depth, 4)
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self.assertEqual(m.init.shape, 8)
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self.assertEqual(len(m.init), 4)
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self.assertEqual(m.attrs, {})
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self.assertEqual(list(m.init), [1, 2, 3, 0])
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def test_constructor_shapecastable(self):
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init = [
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{"a": 0, "b": 1},
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{"a": 2, "b": 3},
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]
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m = memory.Memory(shape=MyStruct, depth=4, init=init, attrs={"ram_style": "block"})
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self.assertEqual(m.shape, MyStruct)
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self.assertEqual(m.depth, 4)
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self.assertEqual(m.attrs, {"ram_style": "block"})
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self.assertIsInstance(m.init, MemoryData.Init)
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self.assertEqual(list(m.init), [{"a": 0, "b": 1}, {"a": 2, "b": 3}, None, None])
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self.assertEqual(m.init._raw, [8, 0x1a, 0, 0])
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def test_constructor_wrong(self):
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with self.assertRaisesRegex(TypeError,
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r"^Memory depth must be a non-negative integer, not 'a'$"):
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memory.Memory(shape=8, depth="a", init=[])
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with self.assertRaisesRegex(TypeError,
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r"^Memory depth must be a non-negative integer, not -1$"):
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memory.Memory(shape=8, depth=-1, init=[])
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with self.assertRaisesRegex(TypeError,
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r"^Object 'a' cannot be converted to an Amaranth shape$"):
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memory.Memory(shape="a", depth=3, init=[])
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with self.assertRaisesRegex(TypeError,
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(r"^Memory initialization value at address 1: "
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r"'str' object cannot be interpreted as an integer$")):
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memory.Memory(shape=8, depth=4, init=[1, "0"])
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with self.assertRaisesRegex(ValueError,
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r"^Either 'data' or 'shape' needs to be given$"):
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memory.Memory(depth=4, init=[])
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with self.assertRaisesRegex(ValueError,
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r"^Either 'data' or 'depth' needs to be given$"):
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memory.Memory(shape=8, init=[])
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with self.assertRaisesRegex(ValueError,
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r"^Either 'data' or 'init' needs to be given$"):
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memory.Memory(shape=8, depth=4)
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data = MemoryData(shape=8, depth=4, init=[])
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with self.assertRaisesRegex(ValueError,
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r"^'data' and 'shape' cannot be given at the same time$"):
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memory.Memory(data, shape=8)
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with self.assertRaisesRegex(ValueError,
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r"^'data' and 'depth' cannot be given at the same time$"):
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memory.Memory(data, depth=4)
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with self.assertRaisesRegex(ValueError,
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r"^'data' and 'init' cannot be given at the same time$"):
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memory.Memory(data, init=[])
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with self.assertRaisesRegex(TypeError,
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r"^'data' must be a MemoryData instance, not 'abc'$"):
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memory.Memory("abc")
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def test_init_set(self):
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m = memory.Memory(shape=8, depth=4, init=[])
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m.init[1] = 2
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self.assertEqual(list(m.init), [0, 2, 0, 0])
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self.assertEqual(m.init._raw, [0, 2, 0, 0])
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m.init[2:] = [4, 5]
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self.assertEqual(list(m.init), [0, 2, 4, 5])
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m.init = [6, 7]
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self.assertEqual(list(m.init), [6, 7, 0, 0])
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def test_init_set_shapecastable(self):
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m = memory.Memory(shape=MyStruct, depth=4, init=[])
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m.init[1] = {"a": 1, "b": 2}
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self.assertEqual(list(m.init), [None, {"a": 1, "b": 2}, None, None])
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self.assertEqual(m.init._raw, [0, 0x11, 0, 0])
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def test_init_set_wrong(self):
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m = memory.Memory(shape=8, depth=4, init=[])
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with self.assertRaisesRegex(TypeError,
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r"^'str' object cannot be interpreted as an integer$"):
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m.init[0] = "a"
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m = memory.Memory(shape=MyStruct, depth=4, init=[])
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# underlying TypeError message differs between PyPy and CPython
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with self.assertRaises(TypeError):
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m.init[0] = 1
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def test_init_set_slice_wrong(self):
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m = memory.Memory(shape=8, depth=4, init=[])
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with self.assertRaisesRegex(ValueError,
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r"^Changing length of Memory.init is not allowed$"):
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m.init[1:] = [1, 2]
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with self.assertRaisesRegex(TypeError,
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r"^Deleting elements from Memory.init is not allowed$"):
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del m.init[1:2]
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with self.assertRaisesRegex(TypeError,
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r"^Inserting elements into Memory.init is not allowed$"):
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m.init.insert(1, 3)
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def test_port(self):
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|
for depth, addr_width in [
|
|
(0, 0),
|
|
(1, 0),
|
|
(3, 2),
|
|
(4, 2),
|
|
(5, 3),
|
|
]:
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|
m = memory.Memory(shape=8, depth=depth, init=[])
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|
rp = m.read_port()
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|
self.assertEqual(rp.signature.addr_width, addr_width)
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|
self.assertEqual(rp.signature.shape, 8)
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|
wp = m.write_port()
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|
self.assertEqual(wp.signature.addr_width, addr_width)
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|
self.assertEqual(wp.signature.shape, 8)
|
|
self.assertEqual(m.read_ports, (rp,))
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|
self.assertEqual(m.write_ports, (wp,))
|
|
|
|
def test_elaborate(self):
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|
m = memory.Memory(shape=MyStruct, depth=4, init=[{"a": 1, "b": 2}])
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|
wp = m.write_port()
|
|
rp0 = m.read_port(domain="sync", transparent_for=[wp])
|
|
rp1 = m.read_port(domain="comb")
|
|
f = m.elaborate(None)
|
|
self.assertIsInstance(f, MemoryInstance)
|
|
self.assertIs(f._data, m.data)
|
|
self.assertEqual(f._data._init._raw, [0x11, 0, 0, 0])
|
|
self.assertEqual(f._write_ports[0]._domain, "sync")
|
|
self.assertEqual(f._write_ports[0]._granularity, 5)
|
|
self.assertIs(f._write_ports[0]._addr, wp.addr)
|
|
self.assertIs(f._write_ports[0]._data, wp.data.as_value())
|
|
self.assertIs(f._write_ports[0]._en, wp.en)
|
|
self.assertEqual(f._read_ports[0]._domain, "sync")
|
|
self.assertEqual(f._read_ports[0]._transparent_for, (0,))
|
|
self.assertIs(f._read_ports[0]._addr, rp0.addr)
|
|
self.assertIs(f._read_ports[0]._data, rp0.data.as_value())
|
|
self.assertIs(f._read_ports[0]._en, rp0.en)
|
|
self.assertEqual(f._read_ports[1]._domain, "comb")
|
|
self.assertEqual(f._read_ports[1]._transparent_for, ())
|
|
self.assertIs(f._read_ports[1]._addr, rp1.addr)
|
|
self.assertIs(f._read_ports[1]._data, rp1.data.as_value())
|
|
self.assertIs(f._read_ports[1]._en, rp1.en)
|
|
|
|
def test_freeze(self):
|
|
m = memory.Memory(shape=unsigned(8), depth=4, init=[])
|
|
m.write_port()
|
|
m.elaborate(None)
|
|
with self.assertRaisesRegex(AlreadyElaborated,
|
|
r"^Cannot add a memory port to a memory that has already been elaborated$"):
|
|
m.write_port()
|
|
with self.assertRaisesRegex(AlreadyElaborated,
|
|
r"^Cannot add a memory port to a memory that has already been elaborated$"):
|
|
m.read_port()
|
|
with self.assertRaisesRegex(AlreadyElaborated,
|
|
r"^Cannot set 'init' on a memory that has already been elaborated$"):
|
|
m.init = [1, 2, 3, 4]
|
|
with self.assertRaisesRegex(AlreadyElaborated,
|
|
r"^Cannot set 'init' on a memory that has already been elaborated$"):
|
|
m.init[0] = 1
|