whitequark a40e2cac4b back.pysim: fix an issue with too few funclet slots.		2018-12-21 10:25:28 +00:00
..
__init__.py	Initial commit.	2018-12-12 03:18:44 +00:00
pysim.py	back.pysim: fix an issue with too few funclet slots.	2018-12-21 10:25:28 +00:00
rtlil.py	back.rtlil: more consistent prefixing for subfragment port wires.	2018-12-21 04:21:11 +00:00
verilog.py	hdl.mem: tie rdport.en high for asynchronous or transparent ports.	2018-12-21 04:22:16 +00:00