whitequark 710a8d0bc1 back.rtlil: ignore empty source locations. ... This was a bug introduced during refactoring in 2492f490.		2019-07-08 09:58:12 +00:00
..
__init__.py	Initial commit.	2018-12-12 03:18:44 +00:00
pysim.py	back.pysim: create unique ResetSynchronizer internal domains.	2019-06-28 08:34:43 +00:00
rtlil.py	back.rtlil: ignore empty source locations.	2019-07-08 09:58:12 +00:00
verilog.py	back.verilog: allow stripping the src attribute, for cleaner output.	2019-04-22 14:59:53 +00:00